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A 5.35 mm2 10GBASE-T Ethernet LDPC Decoder Chip in 90 nm CMOS

Related publications (32)

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A Generalized Adjusted Min-Sum Decoder for 5G LDPC Codes: Algorithm and Implementation

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Yifei Shen, Yuqing Ren, Hassan Harb

5G New Radio (NR) has stringent demands on both performance and complexity for the design of low-density parity-check (LDPC) decoding algorithms and corresponding VLSI implementations. Furthermore, decoders must fully support the wide range of all 5G NR bl ...

Ieee-Inst Electrical Electronics Engineers Inc2024

An All-Digital 1 Mbps, 57 pJ/bit Bluetooth Low Energy (BLE) Backscatter ASIC in 65 nm CMOS

James Daniel Rosenthal

We present an all-digital application specific integrated circuit (ASIC) that implements Bluetooth Low Energy (BLE)-compatible backscatter communication. The ASIC was fabricated in a 65 nm CMOS process and occupies an active area of 0.12 mm(2) while consum ...

IEEE2022

Fast Block Sequential Decoding of Polar Codes

Kirill Ivanov

A reduced complexity sequential decoding algorithm for polar (sub) codes is described. The proposed approach relies on a decomposition of the polar (sub) code being decoded into a number of outer codes, and on-demand construction of codewords of these code ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

From LDPC Block to LDPC Convolutional Codes: Capacity, Stability, and Universality

Wei Liu

In his landmark paper "A Mathematical Theory of Communication," the founding father of information theory and coding theory, Claude E. Shannon, established the largest rate at which reliable communication is possible and he revealed that the key to this re ...

EPFL2019

Design of LDPC Codes for the Unequal Power Two-User Gaussian Multiple Access Channel

Alexios Konstantinos Balatsoukas Stimming

In this letter, we describe an LDPC code design framework for the unequal power two-user Gaussian multiple access channel using EXIT charts. We show that the sumrate of the LDPC codes designed using our approach can get close to the maximal sum-rate of the ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2018

Trading off Energy versus Accuracy in Modern Computing Systems

Jérémy Lucien Maurice Schlachter

The slowdown of Moore's law, which has been the driving force of the electronics industry over the last 5 decades, is causing serious problem to Integrated Circuits (ICs) improvements. Technology scaling is becoming more and more complex and fabrication co ...

EPFL2018

Polar codes are capacity-achieving error-correcting codes with an explicit construction that can be decoded with low-complexity algorithms. In this work, we show how the state-of-the-art low-complexity decoding algorithm can be improved to better accommoda ...

2018

Coding for Communications and Secrecy

Mani Bastaniparizi

Shannon, in his landmark 1948 paper, developed a framework for characterizing the fundamental limits of information transmission. Among other results, he showed that reliable communication over a channel is possible at any rate below its capacity. In 2008, ...

EPFL2017

Hardware implementation aspects of polar decoders and ultra high-speed LDPC decoders

Alexios Konstantinos Balatsoukas Stimming

The goal of channel coding is to detect and correct errors that appear during the transmission of information. In the past few decades, channel coding has become an integral part of most communications standards as it improves the energy-efficiency of tran ...

EPFL2016

Analysis of Spatially Coupled Systems using the Potential Functional with Applications to Coding Theory

Rafah El-Khatib

For the past 70 years or so, coding theorists have been aiming at designing transmission schemes with efficient encoding and decoding algorithms that achieve the capacity of various noisy channels. It was not until the '90s that graph-based codes, such as ...

EPFL2016