Self-Aligned 3D Chip Integration Technology and Through-Silicon Serial Data Transmission
Graph Chatbot
Chat with Graph Search
Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.
DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.
In this paper we propose to eliminate all data and control pads generally present in conventional chips and to replace them with a new type of ultra-compact, low power optical interconnect implemented almost entirely in CMOS. The proposed scheme enables en ...
For the past couple of decades the desire to add more complexity to a computer chip, while simultaneously reducing the cost per bit, has been accommodated by down-scaling. This approach has been extremely successful in the past, but like all good things it ...
With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor Systems-On-Chip (MPSoCs) consisting of complex integrated components communicating with each other at very high-speed rates. Intercommunication ...
Many hardware optimizations rely on collecting information about program behavior at runtime. This information is stored in lookup tables. To be accurate and effective, these optimizations usually require large dedicated on-chip tables. Although technology ...
In this paper, we present an experimental current-mode Kohonen neural network (KNN) implemented in a CMOS 0.18 μm process. The network contains four output neurons. Each neuron has three analog weights related to three inputs. The presented KNN has been re ...
In this paper we propose to replace all data and control pads generally present in conventional chips with a new type of ultra-compact, low-power optical interconnect implemented almost entirely in CMOS. The proposed scheme enables optical through-chip bus ...
Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2008
Nanowire crossbar circuits are an emerging architectural paradigm that promises a higher integration density and an improved fault-tolerance due to its reconfigurability. In this paper, we propose for the first time the utilization of the multi-spacer patt ...
Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs). Networks on Chips (NoCs) are necessary to efficiently handle the 3D interconnect complexity. Desi ...
On-chip implementation of multiprocessor systems needs to planarise the interconnect networks onto the silicon floorplan. Compared with traditional ASIC/SoC architectures, Multiprocessor Systems on Chips (MPSoC) node processors are homogeneous, and MPSoC n ...
