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Design and failure analysis of logic-compatible multilevel gain-cell-based DRAM for fault-tolerant VLSI systems

Related publications (33)

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Multilevel-cell phase-change memory

Aravinthan Athmanathan

In the modern digital era of big data applications, there is an ever-increasing demand for higher memory capacity that is both reliable and cost effective. In the domain of non-volatile memory systems, Flash-based storage devices have dominated the consume ...

EPFL2016

Memory Systems and Interconnects for Scale-Out Servers

Stavros Volos

The information revolution of the last decade has been fueled by the digitization of almost all human activities through a wide range of Internet services. The backbone of this information age are scale-out datacenters that need to collect, store, and proc ...

EPFL2015

Sort vs. Hash Join Revisited for Near-Memory Execution

Babak Falsafi, Boris Robert Grot, Yusuf Onur Koçberber, Nooshin Sadat Mirzadeh

Data movement between memory and CPU is a well-known energy bottleneck for analytics. Near-Memory Processing (NMP) is a promising approach for eliminating this bottleneck by shifting the bulk of the computation toward memory arrays in emerging stacked DRAM ...

2015

Sort vs. Hash Join Revisited for Near-Memory Execution

Babak Falsafi, Boris Robert Grot, Yusuf Onur Koçberber, Nooshin Sadat Mirzadeh

2015

Exploiting NVM in Large-scale Graph Analytics

Willy Zwaenepoel, Jasmina Malicevic

Data center applications like graph analytics require servers with ever larger memory capacities. DRAM scaling, how- ever, is not able to match the increasing demands for ca- pacity. Emerging byte-addressable, non-volatile memory technologies (NVM) offer a ...

2015

A Low-Power Low-Cost 24 GHz RFID Tag With a C-Flash Based Embedded Memory

Adam Shmuel Teman

The key factor in widespread adoption of Radio Frequency Identification (RFID) technology is tag cost minimization. This paper presents the first low-cost, ultra-low power, passive RFID tag, fully integrated on a single substrate in a standard CMOS process ...

Institute of Electrical and Electronics Engineers2014

BuMP: Bulk Memory Access Prediction and Streaming

Babak Falsafi, Boris Robert Grot, Stavros Volos, Javier Picorel Obando

With the end of Dennard scaling, server power has emerged as the limiting factor in the quest for more capable datacenters. Without the benefit of supply voltage scaling, it is essential to lower the energy per operation to improve server efficiency. As th ...

2014

High Sum-Rate Three-Write and Nonbinary WOM Codes

Write-once memory (WOM) is a storage medium with memory elements, called cells, which can take on q levels. Each cell is initially in level 0 and can only increase its level. A t-write WOM code is a coding scheme, which allows one to store t messages to th ...

Institute of Electrical and Electronics Engineers2014

Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology

Georgios Karakonstantis

In this paper, a multi-level wordline driver scheme is presented to improve 6T-SRAM read and write stability. The proposed wordline driver generates a shaped pulse during the read mode and a boosted wordline during the write mode. During read, the shaped p ...

Elsevier2014

Using Managed Runtime Systems to Tolerate Holes in Wearable Memories

James Richard Larus

New memory technologies, such as phase-change memory (PCM), promise denser and cheaper main memory, and are expected to displace DRAM. However, many of them experience permanent failures far more quickly than DRAM. DRAM mechanisms that handle permanent fai ...

ACM2013