Publication

Closing the Gap between FPGA and ASIC

Related publications (112)

About
Privacy
Disclaimer

Graph Chatbot

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

Closing the Gap between FPGA and ASIC

Graph Chatbot

Chat with Graph Search

LUT-Based Optimization For ASIC Design Flow

Logic-in-memory based on an atomically thin semiconductor

A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks

Programmable Logic Gates Based On Tunable Multistable Mechanisms

Reconfigurable Logic Gates Based on Programable Multistable Mechanisms

SAT-Based Exact Synthesis: Encodings, Topology Families, and Parallelism

Reconfigurable logic circuit

SAT-Based Exact Synthesis for Multi-Level Logic Networks

Toward a Full-Flexible and Fast-Prototyping TOF-PET Block Detector Based on TDC-on-FPGA

Finding a Needle in the Haystack of Hardened Interconnect Patterns