Dynamic Resource Allocation for Database Servers Running on Virtual Storage
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Instruction-cache misses account for up to 40%; of execution time in online transaction processing (OLTP) database workloads. In contrast to data cache misses, instruction misses cannot be overlapped with out-of-order execution. Chip design limitations do ...
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Prior research shows that database system performance is dominated by off-chip data stalls, resulting in a concerted effort to bring data into on-chip caches. At the same time, high levels of integration have enabled the advent of chip multiprocessors and ...
User-generated podcasting service over human-centric opportunistic network can facilitate user-generated content sharing while humans are on the move beyond the coverage of infrastructure networks. We focus on the aspects of designing efficient forwarding ...
L1 instruction-cache misses pose a critical performance bottleneck in commercial server workloads. Cache access latency constraints preclude L1 instruction caches large enough to capture the application, library, and OS instruction working sets of these wo ...
We present a consistent and transparent caching system for dynamic web pages produced by a server-side application using a back-end database. Cached pages always reflect current database values. No intervention from the programmer is necessary to implement ...
Cache memories account for a significant fraction of a chip's overall energy dissipation. Recent research advocates using "resizable" caches to exploit cache requirement variability in applications to reduce cache size and eliminate energy dissipation in t ...
Caching is an effective means for reducing load on web servers, especially for those that dynamically generate web documents in J2EE applications. While adding caching to the application server can greatly reduce response times for requests, the logic to e ...
Recent studies have shown that the hardware behavior of database workloads is suboptimal when compared to scientific workloads, and have identified the processor and memory subsystem as the true performance bottlenecks, when running decision-support worklo ...