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Instruction Set Extensions for Cryptographic Hash Functions on a Microcontroller Architecture

Related publications (39)

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Introduction of Local Memory Elements in Synthesis of Instruction Set Extensions

Paolo Ienne

Automatic generation of Instruction Set Extensions (ISEs), executed on a custom processing unit or a coprocessor, is an important step towards processor customization. A typical goal of a manual designer is to combine a large number of atomic instructions ...

2003

Using Cohort-Scheduling to Enhance Server Performance

James Richard Larus

A server application is commonly organized as a collection of concurrent threads, each of which executes the code necessary to process a request. This software architecture, which causes frequent control transfers between unrelated pieces of code, decrease ...

Usenix2002

Democratrizing the Parliament

Rachid Guerraoui

This paper presents a replication algorithm that implements a highly-available, non-deterministic state machine. Our algorithm generalizes the Paxos parliament algorithm of Lamport to cope with non-deterministic computations, while preserving its nice resi ...

2001

Specifying the Semantics of Machine Instructions

Shane Sendall

Computer architecture manuals describe the instruction set of the machine and the semantics of those instructions by a combination of natural language and ISP (Instruction Set Processor) descriptions. The syntax of the instructions in assembly is well defi ...

IEEE Computer Society1998

The compound channel capacity of a class of finite-state channels

Emre Telatar

A transmitter and receiver need to be designed to guarantee reliable communication on any channel belonging to a given family of finite-state channels defined over common finite input, output, and state alphabets. Both the transmitter and receiver are assu ...

1998

Spyder

Christian Iseli

The Spyder project consists of the development of a reconfigurable processor as well as its application development environment. The name Spyder is an anagram of the first letters of "REconfigurable Processor Development SYstem", where the term reconfigura ...

EPFL1996

Evaluation of the SPUR Lisp Architecture

James Richard Larus

The SPUR microprocessor has a 40-bit tagged architecture designed to improve its performance for Lisp programs. Although SPUR includes just a small set of enhancements to the Berkeley RISC-II architecture, simulation results show that with a 150-ns cycle t ...

ACM1986

Optimal State Assignment for Finite State Machines

Giovanni De Micheli

Computer-Aided synthesis of sequential functions of VLSI systems, such as microprocessor control units, must include design optimization procedures to yield area-effective circuits. We model sequential functions as deterministic synchronous Finite State Ma ...

1985

A Comparison of Microcode, Assembly Code, and High-Level Languages on the VAX-11 and RISC I

James Richard Larus

This paper compares the performance of three implementations of simplified pattern matching instruction. The fastest version was microprogrammed on a VAX-11/750, the next fastest was written for a Reduced Instruction Set. Computer (RISC I) developed at Ber ...

ACM1982