Low-Noise, High-Density Microelectronics for Multi-Mode Screening of Excitable Biological Cells

In the past decades, two recording tools have established themselves as the working horses in the field of electrophysiological cell research: the microelectrode array (MEA) and the optical fluorescence imaging. The former is a grid of miniature electrodes allowing to monitor and stimulate cell networks; the latter uses voltage-sensitive dyes (VSDs) rendering the membrane potential visible. So far, researchers trying to combine these two measurement methods face complex electro-optical setups that suffer from the limitations of both techniques. On this ground, it is highly desirable to have a new tool at hand that (a) implements both measurement methods in a single device, (b) offers a high spatio-temporal resolution for both the electrical and the optical sensors, (c) is compact, (d) is easy to handle, and (e) allows long-term measurements. The project, this work is part of, aims to achieve these goals by means of a new concept: the multi-mode sensor array (MMSA). It consists of two parts: (1) a quartz-based microfabricated biointerface housing the sensing devices, i.e. platinum electrodes and amorphous silicon photodiodes; (2) an application specific integrated circuit (ASIC) for the amplification and the conditioning of the detected signals. The two devices are flip-chip bonded together by high-density indium bumps. The resulting measurement tool features a sensor array containing 1024 electrodes and 3072 photodiodes at a pitch of 60 μm and 30 μm, respectively. The main objective of this work is the development of said ASIC with the main task being the design of low-noise, high-density electronic circuits to read the signals detected by the biointerface electrodes and photodiodes. Secondary goals are the packaging of the system and the development of a data acquisition platform to visualise and analyse the measured values. In the course of this dissertation, two ASIC versions were designed: the MMSA I and MMSAII chips. With regard to the electrode low-noise amplifier (LNA), the two versions exhibit substantially different architectures. The MMSAI LNA features a fully-differential architecture, two amplification stages with selectable gain iii Abstract (60/50 dB) and a stable bandwidth of 10 kHz, and two integrated offset compensation techniques. While the measured gain and bandwidth are in good agreement with the simulations, the noise is substantially higher than anticipated since flicker noise was not taken into account in the circuit analysis. Based on the experiences from the MMSA I chip, the second ASIC was developed with a single-ended architecture with a folded-cascode amplifier at its core. It exhibits a gain of 52 dB, a bandwidth of 52 kHz, an average noise of 26 μVrms, and a power consumption of less than 85 μW. The offset compensation allows to deal with input-referred offset in a total range of 40 mV. Furthermore, each pixel was equipped with a sample & hold buffer and a programmable stimulation circuitry. The former stores the amplified signal locally thereby realising an electronic shutter for the electrode signals; the latter is centered around a SRAM (static random access memory) cell and permits the creation of complex stimulation patterns on the array. Comparing the design with literature reveals the competitiveness of the circuit in terms of noise efficiency factor versus area. For the treatment of the photodiode signals, the three-transistor active pixel sensor (APS) architecture is employed due to its simplicity and compactness. To maximise the sensitivity of the sensor, very small transistor dimensions were chosen, thereby minimising the capacitance. The measured responsivity ranges from 0.75 V/μWμs to 0.91 V/μWμs depending on the wavelenght of the incident light. The detectable amplitude can be adjusted by choosing an appropriate integration time. The developed package provides for the biocompatibility of the system, a stable casing, thermal dissipation, a container for the cell culture and nutrient solution, and modularity for easy exchange. The data acquisition platform transfers data at a rate of up to 35 MB/s to a computer via USB 2.0. Furthermore, it offers the creation of protocols to define the course of experiments including the choice of stimulation signal waveform, stimulation patterns, timing information, and recording options.

Microfabricated Multimode Bio-interface with High Density Microelectrode Array and Photonic Detectors

Mohssen Moridi

Presently, the cells' electrical activity is measured either by extracellular microelectrode array (MEA) or by microscopic fluorescence imaging methods. The MEA is a non-invasive in vitro technique which allows long-term recording at multicellular level while fluorescence imaging technique enables to record the cells' action potential from subcellular to the organ level either in vivo or in vitro. These techniques have a number of limitations due to the fact that they require complex electro-optical recording equipment. As a matter of fact, because these systems are expensive, require skilled operators, suffer from problems of keeping the preparations under physiological conditions and permit to conduct only one experiment at a time, they are not suited for long-term and massively parallel measurements. In order to overcome these limitations, it would be highly desirable to obtain a hybrid sensor which combines simultaneous electrical and optical recording capabilities with sufficient spatiotemporal resolution to resolve distributed electrical activity and associated changes in intracellular ion concentrations, both at the single cell level and at the level of entire networks of excitable cells. The objective of this thesis is to design and to fabricate a novel type of hybrid sensor array which allows measuring simultaneously dynamic changes in the extracellular electrical potential and intracellular ion concentrations at a high spatiotemporal resolution. This is realised by a novel approach using a microfabricated glass interface, hereafter called bio-interface, between the electronic readout circuit and the cell network. This bio-interface features an array of 4096 implemented sensing elements, i.e., electrodes and photodiodes, on an area of 3.7 mm2. It is flip-chip bonded to an integrated circuit (IC) by means of high-density indium bumps forming a multi-mode sensor array (MMSA). The IC provides a selectable local amplification of the electrical signals sensed by the microelectrodes, photodetectors, and the processing capabilities to read out all pixels sequentially. The final goal of this work consists of the implementation of a fully operational and validated MMSA measurement platform, which can be used as core instrument for biological research projects. Since the fabricated MMSA essentially represents a microscope-less fluorescence imager with microscopic resolution and embedded electrical signal recording capabilities, it has the potential to turn into a new key measurement technique for both basic and applied biological research in fields as diverse as developmental biology, cardiac electrophysiology, neurophysiology, drug screening, and toxicological studies. This thesis demonstrates the design and fabrication process of the biointerface and the post-processing in connection with the IC and packaging issues. The bio-interface was successfully fabricated and flip-chip bonded to the readout electronics by means of high density indium bumps. These bumps feature a diameter of 15 µm at a 30 µm pitch. Tests show a bump yield of 100 %. The photodiode array was optically characterized and the device biocompatibility was validated by culturing a monolayer of cardiomyocytes on top of the bio-interface.

EPFL2011

Efficiency enhancement and frequency-tunable capability in linear CMOS RF power amplifiers for wireless applications

Paulo Augusto Dal Fabbro

This research work deals with the design of linear CMOS RF power amplifiers. Two important aspects are treated: efficiency enhancement and frequency-tunable capability. For this purpose, two different integrated circuits were realized in a 0.11 µm technology, each one addressing a different aspect. With respect to efficiency enhancement, a dynamic supply RF power amplifier was realized. The circuit was designed for an operating frequency of 5.2 GHz, but measurements were also performed at 2.4 GHz. The integrated circuit includes a class A amplifier and a high-efficiency, switched-mode modulator. It occupies an area of 1.35 mm2. Two-tone measurement results at 2.4 and 5.2 GHz showed that the system can deliver over 16 dBm (40 mW) linear output power with efficiencies of 22.7% and 12.6%, respectively. Compared to a constant 2.5 V supply operation, the power amplifier operating with the dynamic supply delivers higher linear output power. Moreover, a relative efficiency improvement of a factor of 2.3 at 2.4 GHz and of a factor of 1.6 at 5.2 GHz at low output power levels is achieved. OFDM measurements at 2.4 GHz demonstrated that for an EVM lower than 3% and for an equal output power of 11 dBm (12.6 mW), the absolute improvement in efficiency is over 3.2%. In this work we also propose a tunable impedance matching network for use in multiband RF power amplifiers. This novel network is based on coupled inductors. A frequency-tunable RF power amplifier using this network was designed for operation at 3.7 and 5.2 GHz. Simulation results for the complete system integrated in a CMOS technology showed good results. However, the frequency-tunable behavior could not be observed in the characterization of the integrated circuit because of the low coupling factor of the integrated coupled inductors. A hybrid implementation using the integrated CMOS power amplifier, a discrete commercial RF transformer and a discrete bipolar transistor to control the current in the secondary winding of the transformer was carried out. The circuit was designed for operation at 200 and 300 MHz. The measurements have shown that at 200 MHz a relative improvement in efficiency of a factor of 1.4 was achieved. Moreover, less distortion was generated with the proposed tunable output matching network. The hybrid implementation allowed us to demonstrate the feasibility of the frequency-tunable RF power amplifier based on coupled inductors.

EPFL2009

SOI mixed-mode design techniques and case studies

Marija Blagojevic

Since the emergence of Silicon On Insulator (SOI) technology the research activities have been concentrated on a detailed analysis of SOI devices and their use in different application fields (low-voltage, low-power circuits, high temperature electronics, digital circuits, etc.). The present thesis deals with low-voltage, low-power mixed-mode design using a SOI technology. The goal is to establish the concepts that allow one to design SOI mixed-mode circuits, and to apply these concepts to the design of fully depleted (FD) and partially depleted (PD) SOI circuits and systems. Two studies have been realized in the scope of this work: a Hall sensor based microsystem design using an experimental FD SOI technology a DRAM design using capacitor-less 1T floating-body PD SOI memory cells. At the beginning of this thesis, two major types of SOI devices are introduced, namely FD and PD devices. The most important properties of these devices are then presented and compared to those of CMOS bulk devices. A design methodology based on design retargeting from bulk to SOI technology is further proposed. This methodology is developed with the aim of being implemented for the design of FD SOI circuits. It consists in using the same device dimensions and bias currents for the bulk and the corresponding FD SOI design. The analysis performed proves that such an approach permits one to obtain better circuit performances using the FD SOI technology. The EKV model is chosen for Spice simulations. For that purpose the extraction of the EKV intrinsic parameters has been performed for the experimental 0.5 μm FD SOI technology. The EKV model card obtained from transistor measurements is implemented straightforwardly for circuit simulations. The first study presented in this thesis is an FD SOI Hall sensor front-end for energy measurement. The mixed-mode microsystem design is completely based on the proposed design methodology. The system level solutions are also included, such as the spinning-current method that serves for reduction of the offset and low frequency noise of the analog front-end, and a high resolution analog-to-digital conversion technique. The integrated microsystem is entirely functional. Furthermore, according to the existing literature, this integrated circuit is the first microsystem completely realized using FD SOI technology. The overall system error that is obtained is less than 1.5 %. During the second part of this work, a novel sensing scheme that exploits an automatic reference generation based on successive approximations has been developed for the PD SOI capacitor-less 1T DRAM. The 1T DRAM reference current is generated by an adjustable current source. The electrical calibration of the reference current is performed using a digital-to-analog converter and successive approximations algorithm. The proposed scheme is evaluated in a 2 kb test chip. The circuit integrated using PD SOI technology contains a 2 kb 1T memory array, as well as automatic reference generators and peripheral circuits. The automatic reference generator comprises current mode sense amplifier, M/3M converter, and successive approximations register. All blocks implemented in the test chip are described in detail, and PD SOI design issues are discussed. A number of experimental results demonstrate the potential of the PD SOI 1T DRAM for future embedded DRAM applications. The measured retention time under holding conditions is higher than 1s. In the continuous read mode, a few hundreds of the read cycles can be performed without a refresh operation. The test chip has a measured access time of 25 ns with a read cycle time of 70 ns.

EPFL2005