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Design Methods for Parallel Hardware Implementation of Multimedia Iterative Algorithms

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A Novel Approach for Network on Chip Emulation

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Roman Hermida Correa, Nicolas Genko

Current Systems-On-Chip execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solutions. NoCs can have regular or a ...

2005

A Complete Network-On-Chip Emulation Framework

Giovanni De Micheli, David Atienza Alonso, Roman Hermida Correa, Nicolas Genko

Current systems-on-chip (SoC) execute applications that demand extensive parallel processing. Networks-on-chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solutions. NoC can have regular ...

2005

Processeur à haut degré de parallélisme basé sur des composantes sérielles

Ralph Hoffmann

Nowaday, the world of processors is still dominated by the RISC architectures, which foundations have been laid down in the 70's. The RISC concept may be summarized by one word : simplicity. With this concept, much simpler architectures are born, in partic ...

EPFL2004

Adding limited reconfigurability to superscalar processors

Marc Epalza

For the last thirty years, electronics, at first built with discrete components, and then as Integrated Circuits (IC), have brought diverse and lasting improvements to our quality of life. Examples might include digital calculators, automotive and airplane ...

EPFL2004

Dynamically Tuning Processor Resources with Adaptive Processing

Sandhya Dwarkadas

The productivity of modern society has become inextricably linked to its ability to produce energy-efficient computing technology. Increasingly sophisticated mobile computing systems, powered for hours solely by batteries, continue to proliferate rapidly t ...

2003

Load sharing for multiprocessor network nodes

This thesis discusses techniques for sharing the processing load among multiple processing units within systems that act as nodes in a data communications network. Load-sharing techniques have been explored in the field of computer science for many years a ...

EPFL2003

Load Sharing for Multiprocessor Network Nodes

2003

Methods and algorithms for the slicing process in microstereolithography

Philippe Renaud, Arnaud Bertsch

In this paper, methods and algorithms are presented for an efficient slicing process specifically designed for microstereolithography, a high-resolution rapid prototyping technology. Modifications are given for different implementation environments (FPU, P ...

2002

Wisconsin Wind Tunnel II: a fast, portable parallel architecture simulator

Babak Falsafi, James Richard Larus, David Wood

To analyze new, parallel computers, developers must rapidly simulate designs running realistic workloads. Historically, direct execution and a parallel host have accelerated simulations, although these techniques have typically lacked portability. Through ...

2000

SFIO, Parallel File Striping for MPI-I/O

Emin Gabrielyan

SFIO, Parallel File Striping for MPI-I/O Emin Gabrielyan EPFL, Computer Science Dept. Peripheral Systems Lab. Emin.Gabrielyan@epfl.ch Abstract This paper presents the design and evaluation of a Striped File I/O (SFIO) library for parallel I/O in an MPI env ...

2000