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Computing effective properties of random heterogeneous materials on heterogeneous parallel processors

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Evaluating the Suitability of Server Network Cards for Software Routers

Mihai Dobrescu

The advent of multicore CPUs has led to renewed interest in software routers built from commodity PC hardware. However, fully exploiting the parallelism due to multiple cores requires the ability to efficiently parallelize the delivery of packets to cores. ...

2010

Leveraging Parallel Nesting in Transactional Memory

Rachid Guerraoui, Michal Kapalka, Aleksandar Dragojevic

Exploiting the emerging reality of affordable multi-core architectures goes through providing programmers with simple abstractions that would enable them to easily turn their sequential programs into concurrent ones that expose as much parallelism as possi ...

ACM2010

ECC2K-130 on Cell CPUs

Joppe Willem Bos, Thorsten Kleinjung

This paper describes an implementation of Pollard's rho algorithm to compute the elliptic curve discrete logarithm for the Synergistic Processor Elements of the Cell Broadband Engine Architecture. Our implementation targets the elliptic curve discrete loga ...

Springer-Verlag New York, Ms Ingrid Cunningham, 175 Fifth Ave, New York, Ny 10010 Usa2010

PyNEST: a convenient interface to the NEST simulator

Eilif Benjamin Muller, Marc-Oliver Gewaltig

The neural simulation tool NEST (http://www.nest-initiative.org) is a simulator for heterogeneous networks of point neurons or neurons with a small number of compartments. It aims at simulations of large neural systems with more than 10^4 neurons and 10^7 ...

Frontiers Research Foundation2008

Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches

Caches are designed to provide the best tradeoff between access speed and capacity for a set of target applications. Unfortunately, different applications, and even different phases within the same application, may require a different capacity-speed tradeo ...

2007

Tunable 2D Time-Wavelength Optical CDMA Encoder for Differentiated Service Provisioning

Camille Sophie Brès

We propose and demonstrate a reconfigurable tunable encoder for two-dimensional time–wavelength optical code division multiple access (OCDMA). This encoder is capable of creating 2D codes with variable code weight, enabling differentiated service provision ...

Elsevier2007

Reunion: Complexity-effective multicore redundancy

Babak Falsafi

To protect processor logic from soft errors, multicore redundant architectures execute two copies of a program on separate cores of a chip multiprocessor (CMP). Maintaining identical instruction streams is challenging because redundant cores operate indepe ...

2006

A multiprocessor multiwindow visualization subsystem

Roger Hersch

A multiprocessor multiwindow parallel visualization subsystem is presented which can be hooked onto parallel processor arrays of high-speed network interfaces. Thanks to its well-balanced triple transputer architecture, the multiwindow display subsystem is ...

Springer-Verlag1992