Publication
A High-Level Synthesis Flow for the Implementation of Iterative Stencil Loop Algorithms on FPGA Devices
Related publications (47)
Data Structures and Algorithms for Logic Synthesis in Advanced Technologies
Logic synthesis is a key component of digital design and modern EDA tools; it is thus an essential instrument for the design of leading-edge chips and to push the limits of their performance. In the last decades, the electronic circuits community has evolv ...
EPFL2020SAT-Based Exact Synthesis for Multi-Level Logic Networks
Today, the design of electronic systems is largely automated. The practice of using software automation technologies for the design of electronic hardware is commonly referred to as Electronic Design Automation (EDA). EDA comprises a large set of tools, fr ...
EPFL2019An Heterogeneous Compiler Of Dataflow Programs For Zynq Platforms
Marco Mattavelli, Simone Casale Brunet, Romuald Mosqueron, Endri Bezati
In recent years, the number and variety of heterogeneous multiprocessor system-on-chip MPSoCs, such as for instance Zynq platforms, has sensibly increased. However, today all design flow solutions capable of programming the different components of such pla ...
IEEE2019Finding a Needle in the Haystack of Hardened Interconnect Patterns
Paolo Ienne, Grace Zgheib, Stefan Nikolic
Circuits naturally exhibit recurring patterns of local interconnect. Hardening those patterns when designing Field Programmable Gate Array (FPGA) clusters can both eliminate slow programmable connections from the critical path and remove the need for trans ...
IEEE2019FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs
Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Xifan Tang, Edouard Giacomin
In this paper, we developed a simulation-based architecture evaluation framework for field-programmable gate arrays (FPGAs), called FPGA-SPICE, which enables automatic layout-level estimation and electrical simulations of FPGA architectures. FPGA-SPICE can ...
2018Majority Logic Synthesis
Giovanni De Micheli, Mathias Soeken, Luca Gaetano Amarù, Eleonora Testa, Odysseas Zografos
The majority function (xyz) evaluates to true, if at least two of its Boolean inputs evaluate to true. The majority function has frequently been studied as a central primitive in logic synthesis applications for many decades. Knuth refers to the majority f ...
ASSOC COMPUTING MACHINERY2018Circuit Design, Architecture and CAD for RRAM-based FPGAs
Field Programmable Gate Arrays (FPGAs) have been indispensable components of embedded systems and datacenter infrastructures. However, energy efficiency of FPGAs has become a hard barrier preventing their expansion to more application contexts, due to two ...
EPFL2017Leading the Blind
The design and development of innovative FPGA architectures hinge on the flexibility of its toolchain. Retargetable toolchains, like the Verilog-to-Routing (VTR) flow, have been developed to enable the testing of new FPGAs by mapping circuits onto easily-d ...
EPFL2017Exploiting Satisfiability Solvers for Efficient Logic Synthesis
Logic synthesis is an important part of electronic design automation (EDA) flows, which enable the implementation of digital systems. As the design size and complexity increase, the data structures and algorithms for logic synthesis must adapt and improve ...
EPFL2017High level synthesis of Smith-Waterman dataflow implementations
Marco Mattavelli, Simone Casale Brunet, Endri Bezati
The paper presents the results of design explorations for the implementation of the Smith-Waterman (S-W) algorithm executing DNA and protein sequences alignment. Both design explorations studies and the corresponding FPGA implementations are obtained by wr ...
2017