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Everything You Always Wanted to Know about Synchronization but Were Afraid to Ask

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Verification of STM on relaxed memory models

Rachid Guerraoui, Vasu Singh

Software transactional memories (STM) are described in the literature with assumptions of sequentially consistent program execution and atomicity of high level operations like read, write, and abort. However, in a realistic setting, processors use relaxed ...

Springer Verlag2011

The VELOX Transactional Memory Stack

Rachid Guerraoui, Vincent Gramoli, Michal Kapalka, Aleksandar Dragojevic, Pascal Felber

The adoption of multi- and many-core architectures for mainstream computing undoubtedly brings profound changes in the way software is developed. In particular, the use of fine grained locking as the multi-core programmer’s coordination methodology is cons ...

Institute of Electrical and Electronics Engineers2010

Concurrent Programming Paradigms, A Comparison in Scala

Rachid Guerraoui, Martin Odersky, Mohsen Lesani

There is a rapid rise of multi-cores in recent hardware architectures. To exploit computational power of multi-core architectures, software should shift to be as concurrent as possible; and therefore should have concurrency control mechanisms. There are di ...

2009

Software Transactional Memory on Relaxed Memory Models

Rachid Guerraoui, Vasu Singh

Pseudo-code descriptions of STMs assume sequentially consistent program execution and atomicity of high-level STM operations like read, write, and commit. These assumptions are often violated in realistic settings, as STM implementations run on relaxed mem ...

Springer2009

Parallel depth first vs. work stealing schedulers on CMP architectures

Anastasia Ailamaki, Babak Falsafi

In chip multiprocessors (CMPs), limiting the number of off-chip cache misses is crucial for good performance. Many multithreaded programs provide opportunities for constructive cache sharing, in which concurrently scheduled threads share a largely overlapp ...

2006

Software and the Concurrency Revolution

James Richard Larus

Leveraging the full power of multicore processors demands new tools and new thinking from the software industry. Concurrency has long been touted as the "next big thing" and "the way of the future," but for the past 30 years, mainstream software developme ...

ACM2005

Synchronization using failure detectors

Many important synchronization problems in distributed computing are impossible to solve (in a fault-tolerant manner) in purely asynchronous systems, where message transmission delays and relative processor speeds are unbounded. It is then natural to seek ...

EPFL2005

Optimizing traffic in DSM clusters: fine-grain memory caching versus page migration/replication

Babak Falsafi

In this paper we compare and contrast two techniques to improve capacity/conflict miss traffic in CC-NUMA DSM clusters. Page migration/replication optimizes read-write accesses to a page used by a single processor by migrating the page to that processor an ...

2002

Multiplex: Unifying conventional and speculative thread-level parallelism on a chip multiprocessor

Babak Falsafi

Recent proposals for Chip Multiprocessors (CMPs) advocate speculative, or implicit, threading in which the hardware employs prediction to peel off instruction sequences (i.e., implicit threads) from the sequential execution stream and speculatively execute ...

2001

Comparing the effectiveness of fine-grain memory caching against page migration/replication in reducing traffic in DSM clusters

Babak Falsafi

2000