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Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM

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Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM

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Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities

Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM

Gain-Cell Embedded DRAMs: Modeling and Design Space

Data-Retention-Time Characterization of Gain-Cell eDRAMs across the Design and Variations Space

In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA

DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses

A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications

Design Guidelines for High-Performance SCM Hierarchies

An area and power efficient on-the-fly LBCS transformation for implantable neuronal signal acquisition systems

An area and power efficient on-the-fly LBCS transformation for implantable neuronal signal acquisition systems

Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM

Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities

DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses

Design Guidelines for High-Performance SCM Hierarchies

Gain-Cell Embedded DRAMs: Modeling and Design Space

Data-Retention-Time Characterization of Gain-Cell eDRAMs across the Design and Variations Space

An area and power efficient on-the-fly LBCS transformation for implantable neuronal signal acquisition systems

In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA

An area and power efficient on-the-fly LBCS transformation for implantable neuronal signal acquisition systems

A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications