Low Power and Scalable Many-Core Architecture for Big-Data Stream Computing

In the last years the process of examining large amounts of different types of data, or Big-Data, in an effort to uncover hidden patterns or unknown correlations has become a major need in our society. In this context, stream mining applications are now widely used in several domains such as financial analysis, video annotation, surveillance, medical services, traffic prediction, etc. In order to cope with the Big-Data stream input and its high variability, modern stream mining applications implement systems with heterogeneous classifiers and adapt online to its input data stream characteristics variation. Moreover, unlike existing architectures for video processing and compression applications, where the processing units are reconfigurable in terms of parameters and possibly even functions as the input data is changing, in Big-Data stream mining applications the complete computing pipeline is changing, as entirely new classifiers and processing functions are invoked depending on the input stream. As a result, new approaches of reconfigurable hardware platform architectures are needed to handle Big-Data streams. However, hardware solutions that have been proposed so far for stream mining applications either target high performance computing without any power consideration (i.e., limiting their applicability in small-scale computing infrastructures or current embedded systems), or they are simply dedicated to a specific learning algorithm (i.e., limited to run with a single type of classifiers). Therefore, in this paper we propose a novel low-power manycore architecture for stream mining applications that is able to cope with the dynamic data-driven nature of stream mining applications while consuming limited power. Our exploration indicates that this new proposed architecture is able to adapt to different classifiers complexities thanks to its multiple scalable vector processing units and their re-configurability feature at runtime. Moreover, our platform architecture includes a memory hierarchy optimized for Big-Data streaming and implements modern fine-grained power management techniques over all the different types of cores allowing then minimum energy consumption for each type of executed classifier

Energy-Efficient Co-Design Optimization of Many-Core Platforms for Big-Data Streaming Applications

Karim Kanoun

Big-Data streaming applications are used in several domains such as social media analysis, financial analysis, video annotation, surveillance, medical services and traffic prediction. These applications, running on different types of platforms from mobile devices to servers, are characterized by a highly-variable stochastic input data stream, stringent delay constraints and complex task graphs. Several software and hardware optimization techniques have been proposed to maximize the execution quality and the throughput of these applications and to minimize their energy consumption on many-core platforms. By analyzing the existing techniques, one can observe that most solutions classify as a hardware-based task-specific optimization, or as an operating system scheduler optimization, or yet as a load shedding mechanism at the application level. Each of these categories is limited in scope and can be blind to the nature of the program, the data being processed or the characteristics of the hardware. Big-Data streaming applications, due to their wide range of host hardware and content and dynamically-changing input streams, expose the fragmentation of the optimization techniques and create a clear need for a better approach. In this thesis, I propose a suite of energy-efficient hardware-software co-design techniques to bridge the gap between modern Big-Data streaming applications and existing many-core platforms. I choose to model the task graph of the class of applications I consider here by a direct acyclic graph (DAG). First, at the application layer, I propose a unified DAG monitoring solution to process online the general DAG model of the application and provide a set of relevant information that is leveraged at run time by a connected scheduler. At the operating system layer, I propose three different online scheduling solutions for many-core platforms which leverage the feedback from both the application and the hardware layers. The first scheduler addresses the problem of minimizing the energy consumption and the deadlines miss rates of multimedia applications. It takes advantage of the output of the DAG monitoring solution to adapt the mapping of the tasks of multimedia applications to the hardware according to the detected performance and targeted quality of service. The second and third schedulers address the problem of maximizing the quality and throughput and minimizing the energy consumption of Big-Data stream mining applications with single and multiple streams originating from different sources. To cope with the dynamically-changing Big-Data characteristics, the schedulers integrate machine-learning techniques to learn the environment dynamics and the application requirements and adapt the scheduling policy to the desired quality of service. I show that the proposed schedulers are able to scale the execution of data-mining applications to the system capability even in the presence of concept drift. Last, at the hardware layer, to address existing system architectures limitations and to increase even more the throughput, I propose a novel low-power many-core architecture for modern Big-Data stream mining applications that integrates a novel flexible memory hierarchy able to adapt to the dynamic data-driven nature of the input data stream.

EPFL2015

Memory Systems and Interconnects for Scale-Out Servers

Stavros Volos

The information revolution of the last decade has been fueled by the digitization of almost all human activities through a wide range of Internet services. The backbone of this information age are scale-out datacenters that need to collect, store, and process massive amounts of data. These datacenters distribute vast datasets across a large number of servers, typically into memory-resident shards so as to maintain strict quality-of-service guarantees. While data is driving the skyrocketing demands for scale-out servers, processor and memory manufacturers have reached fundamental efficiency limits, no longer able to increase server energy efficiency at a sufficient pace. As a result, energy has emerged as the main obstacle to the scalability of information technology (IT) with huge economic implications. Delivering sustainable IT calls for a paradigm shift in computer system design. As memory has taken a central role in IT infrastructure, memory-centric architectures are required to fully utilize the IT's costly memory investment. In response, processor architects are resorting to manycore architectures to leverage the abundant request-level parallelism found in data-centric applications. Manycore processors fully utilize available memory resources, thereby increasing IT efficiency by almost an order of magnitude. Because manycore server chips execute a large number of concurrent requests, they exhibit high incidence of accesses to the last-level-cache for fetching instructions (due to large instruction footprints), and off-chip memory (due to lack of temporal reuse in on-chip caches) for accessing dataset objects. As a result, on-chip interconnects and the memory system are emerging as major performance and energy-efficiency bottlenecks in servers. This thesis seeks to architect on-chip interconnects and memory systems that are tuned for the requirements of memory-centric scale-out servers. By studying a wide range of data-centric applications, we uncover application phenomena common in data-centric applications, and examine their implications on on-chip network and off-chip memory traffic. Finally, we propose specialized on-chip interconnects and memory systems that leverage common traffic characteristics, thereby improving server throughput and energy efficiency.

EPFL2015

Processeur à haut degré de parallélisme basé sur des composantes sérielles

Ralph Hoffmann

Nowaday, the world of processors is still dominated by the RISC architectures, which foundations have been laid down in the 70's. The RISC concept may be summarized by one word : simplicity. With this concept, much simpler architectures are born, in particular from their instruction sets point of view. As a result, these architectures have a more efficient instruction decoding and smaller computing units which in turn provides the ability to have more of these units for the same price, a reduced clock per instruction ratio — a single cycle per instruction ideally — and increased clock frequencies. As time goes by, RISC architectures have shown outstanding performances, on one hand with the spectacular improvements of semiconductor technologies, and on the other hand with the use of large cache memories and with the development of new ways of execution such as speculative execution. Later developments have greatly altered the original spirit of the simplicity of the RISC concept. Current high performance processors are extremely complex and difficult to design. Moreover, semiconductor technologies begin to show serious problems ignored or neglected for a long time. In this thesis, we would like to introduce a new architecture. Two complementary aspects have been taken in consideration : the design of the processor's units (arithmetic operators, control logic, and so on) and the architectural model, the way the processing units are used. The first aspect has been addressed with an unusual and original approach which involves the use of the serial arithmetic principles. Serial arithmetic tends to reduce the hardware cost, enables higher clock rates, and shows interesting properties which will be developped later on. The research of an architectural model is driven by the same wish of simplicity, recurrent in this field, and will inevitably shift the complexity from the processor to the compiler. This simplification relies on two things : first, the way we think of the problem is inspired by the EPIC philosophy (Explicitly Parallel Instruction Computer), the latest offspring of the VLIW model which advocates the delegation of decisions from the hardware to the software. In one sentence, "the compiler decides, the hardware executes". Second, the way we act has been given by the TTA model (Transport Triggered Architecture), the last offspring of the MOVE model which not only removes from the processor the responsability to decide which processing unit to be used for each instruction (it's already the case in a VLIW processor), but also releases the processor from scheduling the data flows. In doing so, the processor is confined to provide a set of computing units, storage units and means of communication, and the compiler decides how to move the data. In this way, a part of the control logic is removed, communication resources may be fine-tuned and the compiler's code-optimization can be enhanced. With the combination of those elements, we wish to get an architecture which exhibits a better computing power/consumption ratio, which is more flexible, easier to developp and to evolve.

EPFL2004

Processeur à haut degré de parallélisme basé sur des composantes sérielles

Ralph Hoffmann

EPFL2004

Energy-Efficient Co-Design Optimization of Many-Core Platforms for Big-Data Streaming Applications

Karim Kanoun

EPFL2015

Memory Systems and Interconnects for Scale-Out Servers

Stavros Volos

EPFL2015