Cost-Effective Design of Mesh-of-Tree Interconnect for Multi-Core Clusters with 3-D Stacked L2 Scratchpad Memory
Graph Chatbot
Chat with Graph Search
Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.
DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.
This paper presents a highly sensitive photo-detector array deposited on a glass substrate with an integrated optical filter. The active element is a vertically integrated hydrogenated amorphous silicon photodiode featuring a dark current of less than 1e-1 ...
A new approach for inserting repeaters in 3-D interconnects is proposed. The allocation of repeaters along an interplane interconnect is iteratively determined. The proposed approach is compared with two other techniques based on conventional methods used ...
We are witnessing a growing interest in Networks on Chips (NoC) that is related to the evolution of integrated circuit technology and to the growing requirements in performance and portability of electronic systems. Current integrated circuits contain seve ...
In this paper, the partially depleted SOI phototransistor has been used as a light intensity sensor. A pixel implementing the technique elaborated in [1] was designed and implemented on SOI technology. The circuit implements a first order delta-sigma modul ...
Accurate statistical modeling and simulation are keys to ensure that integrated circuits (ICs) meet specifications over the stochastic variations inherent in IC manufacturing technologies. Backward propagation of variance (BPV) is a general technique for s ...
In this paper we propose to eliminate all data and control pads generally present in conventional chips and to replace them with a new type of ultra-compact, low power optical interconnect implemented almost entirely in CMOS. The proposed scheme enables en ...
We demonstrate high-performance nanowire superconducting single photon detectors (SSPDs) on bN thin films grown at a temperature compatible with monolithic integration. NbN films ranging from 150nm to 3nm in thickness were deposited by dc magnetron sputter ...
Field-enhanced sample stacking, field-enhanced sample injection as well as electrokinetic supercharging have been successfully integrated in carrier ampholyte-based capillary electrophoresis. Through the analysis of different test sample mixtures, it has b ...
In this paper we propose to replace all data and control pads generally present in conventional chips with a new type of ultra-compact, low-power optical interconnect implemented almost entirely in CMOS. The proposed scheme enables optical through-chip bus ...
Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2008
Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs). Networks on Chips (NoCs) are necessary to efficiently handle the 3D interconnect complexity. Desi ...