1T Capacitor-less DRAM cell based on asymmetric Tunnel FET design
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This paper presents a methodology of a basic analog blocks retargeting from bulk to fully depleted (FD) SOI technology. The design methodology is generally not related to the model used for the circuit simulations. However, the proposed one is closely link ...
Direct observation of polarization distribution at nanoscale by scanning force microscopy across partially etched Pb(Zr,Ti)O-3 film ferroelectric capacitors with size 2x3 mum and preferential orientation (111) has revealed an anomalous polarization pattern ...
We investigate the equivalent oxide thickness of a thin oxide interlayer in gate insulator stacks on silicon. Through the use of a first-principles approach, we map the profile of the local permittivity across two interface models showing different suboxid ...
Capacitors in metal-insulator-metal structure have been fabricated with different bottom electrodes. It has been found that the observed losses are enormous at gigahertz frequencies unless due care is taken not only for the conductivity of the bottom elect ...
Since the emergence of Silicon On Insulator (SOI) technology the research activities have been concentrated on a detailed analysis of SOI devices and their use in different application fields (low-voltage, low-power circuits, high temperature electronics, ...
