Modeling Minority Carriers Related Capacitive Effects for Transient Substrate Currents in Smart Power ICs

This paper presents an extended model for transient and ac circuit-level simulation of minority carriers propagation through the substrate of smart power integrated circuits (ICs). A p-n junction and a diffusion resistor with capacitive components are proposed to efficiently simulate transient parasitic coupled currents in high-power stages. From a general chip layout, an equivalent substrate network including capacitive effects (junction and diffusion capacitances) can be extracted and parasitic bipolar transistor can be simulated for the first time in transient operation by circuit simulators once the minority carriers continuity conditions are satisfied. This paper shows simulation results of the implemented models in good agreement with those obtained from technology computer-aided design. This implies that transient layout dependent mechanisms between high-voltage aggressor wells and low-voltage victims can be verified in early stages of IC design flow.

Spice-compatible modeling of high injection and propagation of minority carriers in the substrate of Smart Power ICs

Pietro Buccella, Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci

Classical substrate noise analysis considers the silicon resistivity of an integrated circuit only as doping dependent besides neglecting diffusion currents as well. In power circuits minority carriers are injected into the substrate and propagate by drift diffusion. In this case the conductivity of the substrate is spatially modulated and this effect is particularly important in high injection regime. In this work a description of the coupling between majority and minority drift diffusion currents is presented. A distributed model of the substrate is then proposed to take into account the conductivity modulation and its feedback on diffusion processes. The model is expressed in terms of equivalent circuits in order to be fully compatible with circuit simulators. The simulation results are then discussed for diodes and bipolar transistors and compared to the ones obtained from physical device simulations and measurements. (C) 2014 Published by Elsevier Ltd.

Elsevier2015

Efficiency enhancement and frequency-tunable capability in linear CMOS RF power amplifiers for wireless applications

Paulo Augusto Dal Fabbro

This research work deals with the design of linear CMOS RF power amplifiers. Two important aspects are treated: efficiency enhancement and frequency-tunable capability. For this purpose, two different integrated circuits were realized in a 0.11 µm technology, each one addressing a different aspect. With respect to efficiency enhancement, a dynamic supply RF power amplifier was realized. The circuit was designed for an operating frequency of 5.2 GHz, but measurements were also performed at 2.4 GHz. The integrated circuit includes a class A amplifier and a high-efficiency, switched-mode modulator. It occupies an area of 1.35 mm2. Two-tone measurement results at 2.4 and 5.2 GHz showed that the system can deliver over 16 dBm (40 mW) linear output power with efficiencies of 22.7% and 12.6%, respectively. Compared to a constant 2.5 V supply operation, the power amplifier operating with the dynamic supply delivers higher linear output power. Moreover, a relative efficiency improvement of a factor of 2.3 at 2.4 GHz and of a factor of 1.6 at 5.2 GHz at low output power levels is achieved. OFDM measurements at 2.4 GHz demonstrated that for an EVM lower than 3% and for an equal output power of 11 dBm (12.6 mW), the absolute improvement in efficiency is over 3.2%. In this work we also propose a tunable impedance matching network for use in multiband RF power amplifiers. This novel network is based on coupled inductors. A frequency-tunable RF power amplifier using this network was designed for operation at 3.7 and 5.2 GHz. Simulation results for the complete system integrated in a CMOS technology showed good results. However, the frequency-tunable behavior could not be observed in the characterization of the integrated circuit because of the low coupling factor of the integrated coupled inductors. A hybrid implementation using the integrated CMOS power amplifier, a discrete commercial RF transformer and a discrete bipolar transistor to control the current in the secondary winding of the transformer was carried out. The circuit was designed for operation at 200 and 300 MHz. The measurements have shown that at 200 MHz a relative improvement in efficiency of a factor of 1.4 was achieved. Moreover, less distortion was generated with the proposed tunable output matching network. The hybrid implementation allowed us to demonstrate the feasibility of the frequency-tunable RF power amplifier based on coupled inductors.

EPFL2009

Optimization Strategy of Numerical Simulations Applied to EPFL Substrate Model

Pietro Buccella, Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci

A new methodology for modeling minority carriers diffusion in Smart Power ICs substrate using standard circuit simulators has been proposed by EPFL. For this purpose, a parasitic substrate network consisting of lumped elements is extracted from the circuit layout following a given substrate meshing strategy. In this work Design of Experiments (DOE) techniques are used to run a limited number of simulations to evaluate the influence of the meshing on the accuracy of the EPFL Substrate Model when compared to finite element simulations. A two-dimensional case study on a parasitic lateral bipolar is then proposed with both spice-like and finite element simulation results for the minority carriers diffusion. A linear model is developed to estimate the most important geometrical domains influencing the accuracy of the studied model.

Ieee2014

Efficiency enhancement and frequency-tunable capability in linear CMOS RF power amplifiers for wireless applications

Paulo Augusto Dal Fabbro

EPFL2009