Memory Systems and Interconnects for Scale-Out Servers
Graph Chatbot
Chat with Graph Search
Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.
DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.
With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor Systems-On-Chip (MPSoCs) consisting of complex integrated components communicating with each other at very high-speed rates. Intercommunication ...
In this paper, we present an experimental current-mode Kohonen neural network (KNN) implemented in a CMOS 0.18 μm process. The network contains four output neurons. Each neuron has three analog weights related to three inputs. The presented KNN has been re ...
The aim of the present invention is to propose a method to provide reliability, power management and load balancing support for multicore systems based on Networks- on-Chip (NoCs) as well as a way to efficiently implement architectural support for this met ...
To tackle the increasing communication complexity of multi-core systems, scalable Networks on Chips (NoCs) are needed to interconnect the processor, memory and hardware cores of the systems. For the use of NoCs to be feasible in today's industrial designs, ...
Many hardware optimizations rely on collecting information about program behavior at runtime. This information is stored in lookup tables. To be accurate and effective, these optimizations usually require large dedicated on-chip tables. Although technology ...
A low power, current-mode memory element for analog discrete time iterative decoders is proposed. In the circuit a high-speed power-down mechanism has been implemented that enables a significant increase of the operation speed without increasing the power ...
On-chip implementation of multiprocessor systems needs to planarise the interconnect networks onto the silicon floorplan. Compared with traditional ASIC/SoC architectures, Multiprocessor Systems on Chips (MPSoC) node processors are homogeneous, and MPSoC n ...
Currently, software engineering is becoming even more complex due to distributed computing. In this new context, portability while providing the programmer with the single system image of a classical Java Virtual Machine (JVM) is one of the key issues. Hen ...
Because the market has an insatiable appetite for new functionality, performance is becoming an increasingly important factor. The telecommunication and network domains are especially touched by this phenomenon but they are not the only ones. For instance, ...
Instruction Set Extensions (ISEs) can be used effectively to accelerate the performance of embedded processors. The critical, and difficult task of ISE selection is often performed manually by designers. A few automatic methods for ISE generation have show ...