Publication
Dataflow Programs Analysis and Optimization Using Model Predictive Control Techniques. Two Examples of Bounded Buffer Scheduling: Deadlock Avoidance and Deadlock Recovery Strategies
Related publications (38)
Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms
Aurélien François Gilbert Bloch
Today's continued increase in demand for processing power, despite the slowdown of Moore's law, has led to an increase in processor count, which has resulted in energy consumption and distribution problems. To address this, there is a growing trend toward ...
EPFL2023Design Space Exploration for Partitioning Dataflow Program on CPU-GPU Heterogeneous System
Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch
Dataflow programming is a methodology that enables the development of high-level, parametric programs that are independent of the underlying platform. This approach is particularly useful for heterogeneous platforms, as it eliminates the need to rewrite ap ...
SPRINGER2023SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis
Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch
Writing and optimizing application software for heterogeneous platforms including GPU units is a very difficult task that requires designer efforts and resources to consider several key elements to obtain good performance. Dataflow programming has shown to ...
2022Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms by Dynamic Network Execution
Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch
The performance of programs executed on heterogeneous parallel platforms largely depends on the design choices regarding how to partition the processing on the various different processing units. In other words, it depends on the assumptions and parameters ...
MDPI2022Inter-actions parallel execution on GPU from high-level dataflow synthesis
Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch
Recent GPU architectures make available numbers of parallel processing units that exceed by orders of magnitude the ones offered by CPU architectures. Whereas programs written using dataflow programming languages are well suited for programming heterogeneo ...
IEEE2022Composite Data Types in Dynamic Dataflow Languages as Copyless Memory Sharing Mechanism
Marco Mattavelli, Endri Bezati, Aurélien François Gilbert Bloch
This paper presents new optimization approaches aiming at reducing the impact of memory accesses on the performance of dataflow programs. The approach is based on introducing a high level management of composite data types in dynamic dataflow programming l ...
2019High-Precision Performance Estimation for the Design Space Exploration of Dynamic Dataflow Programs
Marco Mattavelli, Simone Casale Brunet, Endri Bezati, Malgorzata Maria Michalska
The implementation and optimization of dynamic dataflow programs on multi/many-core platforms require solving a very difficult problem: how to partition and schedule the processing elements and dimension their interconnecting buffers according to given opt ...
2018Execution Trace Graph of Dataflow Process Networks
Marco Mattavelli, Simone Casale Brunet
The paper introduces and specifies a formalism that provides complete representations of dataflow process network (DPN) program executions, by means of directed acyclic graphs. Such graphs, also known as execution trace graphs (ETG), are composed of nodes ...
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2018Buffer dimensioning for throughput improvement of dynamic dataflow signal processing applications on multi-core platforms
Marco Mattavelli, Simone Casale Brunet, Endri Bezati, Malgorzata Maria Michalska
Executing a dataflow program on a parallel platform requires assigning to each buffer a given size so that correct program executions take place without introducing any deadlock. Furthermore, in the case of dynamic dataflow programs, specific buffer size a ...
2017Systematic Design Space Exploration of Dynamic Dataflow Programs for Multi-core Platforms
The limitations of clock frequency and power dissipation of deep sub-micron CMOS technology have led to the development of massively parallel computing platforms. They consist of dozens or hundreds of processing units and offer a high degree of parallelism ...
EPFL2017