A nA Crystal - Less Oscillator for Internet of Things

This work presents an ultra-low power oscillator designed to target different contexts, such as crystal-assisted time keeping, reference oscillator to optimize the always on domain of a microcontroller or wake-up timer. This oscillator enables ultra-low power operation in 0.18 mu m CMOS technology; the core oscillator consumes 2.5 nW at room temperature, with a temperature stability of 14 ppm/degrees C [-40 degrees C -60 degrees C] and 0.07 %/V supply sensitivity.

Optimization of the Data Rate of an OOK CMOS Medical Transmitter Based on LC Oscillators

Catherine Dehollain, Franco Maloberti, Kerim Türe, Gürkan Yilmaz

This paper presents techniques for increasing communication data rates for OOK modulated signals in the case the carrier frequency is generated by a cross-coupled pair LC oscillator. The proposed circuitry completely turns off the transmitter during the transmission of "0" bit and oscillation occurs only when the data bit is "1" to reduce power consumption. The data bit controls the steady state bias current and the operation of the oscillator. The communication data rate is limited by the turn-on and turn-off time of the LC oscillator. In order to speed up the turn-on time of the oscillator, in addition to bias current, an extra current source is used during the build-up of the oscillator. The decay time of the oscillator when the data is switched from "1" to "0" is accelerated by shortening the inductor connections. The concept is demonstrated through the design of an LC VCO in 0.18 mu m CMOS technology. The LC oscillator is designed to oscillate in MedRadio band at 416 MHz frequency. Simulation results show that the proposed architecture shortens the turn-on time from 86.5 ns to 24 ns and the turn-off time from 101 ns to 5.93 ns. With the additional techniques, the maximum achievable communication data rate is increased by more than 6 times.

Ieee2016

Electron Spin Resonance detectors from 400 MHz to 360 GHz

Alessandro Valentino Matheoud

Methods based on the electron spin resonance (ESR) phenomenon are non-invasive tools adopted to investigate paramagnetic systems at temperatures ranging from above 1000 K to below 1 K. Since 2008, the group of Dr. Boero has been working on a detection technique based on the integration of ESR sensors on single chips. The proposed methodology allowed to study samples in the nanoliter scale and reach a spin sensitivity at least two orders of magnitude better than the best commercially available spectrometers. The detection principle can be summarized as follows. An ESR sensitive sample is placed in close proximity to the planar inductor of an LC oscillator operating at microwave frequency. In presence of a suitable static magnetic field, the ESR phenomenon takes place. It causes a variation in the sample magnetization which translates to a variation of the inductance, leading to both a frequency shift of the oscillator (frequency detection) and a variation of the oscillation amplitude (amplitude detection). Consequently, the ESR phenomenon may be detected by tracking the operating point of the oscillator. In this thesis, I investigate the application of the aforementioned detection principle in the range from 400 MHz to 360 GHz. Firstly, a semi-integrated solution operating from 400 MHz to 610 MHz is developed for an industrial application (CTI project). In such context, the originality of the work stands in the implementation of a completely standalone portable scanner for contactless inspection which may also be used for ferromagnetic (FMR) applications and zero-field measurements. Secondly, a set of single-chip ESR detectors working from 10 GHz to 146 GHz and based on CMOS technologies are characterized from 300 K down to 10 K. Here, an ESR experiment at a frequency as high as 360 GHz can be performed thanks to the fourth harmonic signal generated by a 90 GHz detector. Conversely, the 10 GHz detector shows the best noise performance and allows to achieve the record distance resolution of 0.3 pm when used as a proximity sensor. After that, the possibility of using integrated technologies based on HEMTs is investigated so as to overcome the main limitations of the CMOS based detectors: (1) the high power consumption which denies their use below 10 K and (2) the saturation issue due to the magnitude of the intrinsic microwave magnetic field produced by the oscillators. In this context, two HEMT oscillators working at 11 GHz and 25 GHz are realized. In particular, the former achieves the record minimum power consumption (90 uW at 300 K and 4 uW below 30 K) currently reported in the literature for oscillators working in the same frequency range. Also, the proposed sensor achieves a minimum microwave magnetic field of less than 1 uT at 300 K and less than 0.1 uT below 30 K, i.e., orders of magnitude below the values achieved with previous CMOS detectors. Furthermore, an analytical model is carried out in order to estimate the minimum achievable power consumption for an LC single-ended Colpitts oscillator based on any single FET. Lastly, the DC characterization of a standing alone HEMT transistor is provided from 300 K down to 1.4 K, ranging from the standard Ids-Vs-Vds curves to the extraction of both the number of carriers and their effective mobility. The former comes from the analysis of the Shubnikov-de-Haas oscillations whereas the latter is calculated by means of Hall-effect based experiments.

EPFL2019

Low power frequency synthesizer for mobile communications systems

Imre Kovacs

A novel frequency synthesizer with a strong emphasis on low-power consumption (2mW) was developed for this thesis. A BAW-resonator was used for the design of the high-frequency oscillator. The BAW's high Q-Factor ensured a minimal power consumption, while providing outstanding phase noise performance. This type of frequency synthesizer can be implemented in practically every mobile wireless system standard, which is relying on batteries as the power supply, such as Bluetooth, Zigbee and others. For this work, a Bluetooth-compatible standard was taken in order to derive the system specifications. The frequency synthesizer then was designed and implemented in a 180nm CMOS process. The approach of the "Sliding-IF" architecture was chosen and modified in order to take full advantage on the BAW oscillator. Therefore a two-stage frequency translation of the signal was necessary, similar to the super-heterodyne transceiver topology. The channel selection and the frequency error correction is done at the second stage, since the BAW-based oscillator does practically not provide any frequency tuning. For this, a Delta-Sigma-Modulator based Fractional-N PLL was developed. A system supply voltage of 1.2V was chosen in order to keep power consumption as low as possible. This supply voltage can also be easily supplied by AA or AAA-batteries and a low-voltage regulator. The most important technique to reduce overall power consumption was to reduce the high-frequency requirements to the system blocks. This was done by modifying the "Sliding-IF" architecture and by the use of the BAW resonator. The minimization of the power consumption required careful choice and design of each of the system blocks. For this, several approaches were analyzed, especially the topology of each block and its optimization were important. A special emphasis on the analysis, design and discussion was also made on the noise, and especially the phase noise. A ring oscillator, a LC-VCO and a BAW-oscillator were implemented and measured in order to validate the theory and the simulation results. The complete frequency synthesizer with an Automatic Amplitude Control, Frequency Dividers, Mixer, Charge-Pump, Phase-Frequency Detector and a Delta-Sigma-Modulator was designed and implemented. This thesis was elaborated in the frame of the MiNAMI and MiMOSA projects of the European research programme (FP6).