Publication

A 60 Gb/s 1.9 pJ/bit NRZ Optical-Receiver with Low Latency Digital CDR in 14nm CMOS FinFET

Related publications (46)

Energy-Efficient Design Techniques for High-Speed Wireline Serial Links

The exponential growth in computing power and multimedia services has caused a tremendous increase in data traffic in recent years. This increase in data traffic brings a strong demand for data bandwidth of electrical input/output (I/O) links and pushes th ...

EPFL2021

Demonstration of Tunable Optical Aggregation of QPSK to 16-QAM Over Optically Generated Nyquist Pulse Trains Using Nonlinear Wave Mixing and a Kerr Frequency Comb

Tobias Kippenberg, Maxim Karpov, Martin Hubert Peter Pfeiffer, Arne Kordts, Fatemeh Alishahi, Ahmad Fallahpour, Cong Liu

A tunable and reconfigurable optical aggregation system is experimentally demonstrated. Optical Nyquist pulses are generated on multiple channels using a microresonator-based Kerr optical frequency comb and insertion of uniform lines by an intensity modula ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

Kramers Kronig detection of four 20 Gbaud 16-QAM channels using Kerr combs for a shared phase estimation

Tobias Kippenberg, Maxim Karpov, Martin Hubert Peter Pfeiffer, Arne Kordts, Fatemeh Alishahi, Ahmad Fallahpour

We experimentally demonstrate Kramers-Kronig detection of four 20 Gbaud 16-quadrature-amplitude-modulated (QAM) channels after 50 km fiber transmission using two soliton Kerr combs as signal sources and local oscillators. The estimated carrier phase at the ...

OPTICAL SOC AMER2020

A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

Andreas Peter Burg, Cosimo Aprile, Yusuf Leblebici, Alessandro Cevrero, Lukas Kull, Gain Kim, Ilter Ozkaya, Thomas Toifl

This article introduces a wireline receiver (RX) data-path employing discrete multi-tone (DMT) modulation for communicating over electrical links. The DMT RX incorporates a fully digital equalization data-path, with a synthesized and automatically placed a ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

ISI Sensitivity of PAM Signaling for Very High-Speed Short-Reach Copper Links

Seyed Armin Tajalli, Yusuf Leblebici, Firat Çelik, Ayça Akkaya

This paper presents a comparative study, analyzing the potentials of pulse amplitude modulation (PAM) for implementing next generation high-speed copper wireline links. This comparative study analyzes the sensitivities of PAM2, PAM4 and PAM8 to inter-symbo ...

IEEE2019

Experimental demonstration of three-fold wavelength multicasting of a 64-QAM 120 Gbit/s data channel using a Kerr frequency comb and nonlinear wave mixing

Tobias Kippenberg, Maxim Karpov, Martin Hubert Peter Pfeiffer, Arne Kordts, Fatemeh Alishahi, Ahmad Fallahpour

We experimentally demonstrate three-fold wavelength multicasting of a 64-quadrature-amplitude-modulation (QAM), 120-Gbit/s data channel using a microresonator Kerr frequency comb and nonlinear wave mixing. The multicasting is achieved with a data signal an ...

SPIE-INT SOC OPTICAL ENGINEERING2019

Design Considerations and Performance Trade-Offs for 56Gb/s Discrete Multi-Tone Electrical Link

Yusuf Leblebici, Gain Kim, Thomas Toifl

For communicating over mid-to-long-reach electrical links at a data-rate above 56Gb/s, ADC-based receiver (RX) has become a dominant architecture due to its strong equalization capability using complex digital signal processing algorithm benefiting from th ...

IEEE2019

Adaptive Receiver Design for High Speed Optical Communication

Ilter Ozkaya

Conventional input/output (IO) links consume power, independent of changes in the bandwidth demand by the system they are deployed in. As the system is designed to satisfy the peak bandwidth demand, most of the time the IO links are idle but still consumin ...

EPFL2018

Multi-Tone Signaling and ADC-Based Digital Receiver for High-Speed Wireline Serial Links

Gain Kim

The exponential growth of Internet traffic and related demands for higher communication speed pushes processor-to-processor and processor-to-memory interconnects to provide further higher data-rate. Often time, processor-to-memory interconnectsâ speed is ...

EPFL2018

Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders

Andreas Peter Burg, Lukas Kull, Thomas Toifl, Giovanni Cherubini

The implementation of a 25.6-Gb/s four-level pulse-amplitude-modulation (4-PAM) reduced-state sliding-block Viterbi detector (VD) is presented. The power consumption of the VD is 105 orilV at a supply voltage of 0.7 V, corresponding to an energy efficiency ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2018

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