Publications related to RM3 based logic synthesis

Integrated ESOP Refactoring for Industrial Designs

Giovanni De Micheli, Mathias Soeken, Luca Gaetano Amarù, Winston Jason Haaswijk

We present a multi-level logic refactoring algorithm based on exclusive sum-of-product (ESOP) expressions. ESOP expressions are two-level logic representation forms, similar to sum of -product (SOP) expressions. However, ESOPs use EXOR instead of OR operat ...

IEEE2018

Majority Logic Synthesis

Giovanni De Micheli, Mathias Soeken, Luca Gaetano Amarù, Eleonora Testa, Odysseas Zografos

The majority function (xyz) evaluates to true, if at least two of its Boolean inputs evaluate to true. The majority function has frequently been studied as a central primitive in logic synthesis applications for many decades. Knuth refers to the majority f ...

ASSOC COMPUTING MACHINERY2018

SAT Based Exact Synthesis using DAG Topology Families

Giovanni De Micheli, Mathias Soeken, Winston Jason Haaswijk

SAT based exact synthesis is a powerful technique, with applications in logic optimization, technology mapping, and synthesis for emerging technologies. However, its runtime behavior can be unpredictable and slow. In this paper, we propose to add a new typ ...

IEEE2018

Exact Synthesis for Logic Synthesis Applications with Complex Constraints

Giovanni De Micheli, Mathias Soeken, Eleonora Testa, Odysseas Zografos

Exact synthesis is the problem of finding logic networks that represent given Boolean functions and respect given constraints. With exact synthesis it is possible to find optimum networks, e.g., in size or depth; consequently, it primarily finds applicatio ...

2017

A Compiler for Parallel and Resource-Constrained Programmable in-Memory Computing

Giovanni De Micheli, Mathias Soeken, Pierre-Emmanuel Julien Marc Gaillardon, Giulia Meuli

Solid-state resistive switches have recently enabled low-power, scalable, non-volatile memories. Their proven intrinsic logic operation, allowing design of in-memory computing systems, attracted the attention of the research community. A Programmable Logic ...

2017

Multi-level Logic Benchmarks: An Exactness Study

Giovanni De Micheli, Mathias Soeken, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù, Eleonora Testa, Winston Jason Haaswijk

In this paper, we study exact multi-level logic benchmarks. We refer to an exact logic benchmark, or exact benchmark in short, as the optimal implementation of a given Boolean function, in terms of minimum number of logic levels and/or nodes. Exact benchma ...

Ieee2017

Majority-based Synthesis for Nanotechnologies

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

We study the logic synthesis of emerging nanotechnologies whose elementary devices abstraction is a majority voter. We argue that synthesis tools, natively supporting the majority logic abstraction, are the technology enablers. This is because they allow d ...

Ieee2016

SAT-Based Combinational and Sequential Dependency Computation

Giovanni De Micheli, Mathias Soeken

We present an algorithm for computing both functional dependency and unateness of combinational and sequential Boolean func- tions represented as logic networks. The algorithm uses SAT-based tech- niques from Combinational Equivalence Checking (CEC) ...

Springer2016

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RM3 based logic synthesis

Integrated ESOP Refactoring for Industrial Designs

Majority Logic Synthesis

SAT Based Exact Synthesis using DAG Topology Families

Exploiting Satisfiability Solvers for Efficient Logic Synthesis

Exact Synthesis for Logic Synthesis Applications with Complex Constraints

A Compiler for Parallel and Resource-Constrained Programmable in-Memory Computing

Multi-level Logic Benchmarks: An Exactness Study

Majority-based Synthesis for Nanotechnologies

Automatic Generation of Efficient Accelerators for Reconfigurable Hardware

SAT-Based Combinational and Sequential Dependency Computation

Graph Chatbot

Chat with Graph Search

Automatic Generation of Efficient Accelerators for Reconfigurable Hardware

A Compiler for Parallel and Resource-Constrained Programmable in-Memory Computing

Exploiting Satisfiability Solvers for Efficient Logic Synthesis

Integrated ESOP Refactoring for Industrial Designs

Majority Logic Synthesis

SAT Based Exact Synthesis using DAG Topology Families

SAT-Based Combinational and Sequential Dependency Computation

Majority-based Synthesis for Nanotechnologies

Exact Synthesis for Logic Synthesis Applications with Complex Constraints

Multi-level Logic Benchmarks: An Exactness Study