Design Space Exploration Problem Formulation for Dataflow Programs on Heterogeneous Architectures, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC)

The implementations of signal processing systems on the emerging many-core or multi-core processing platforms require to solve a very difficult problem: how to partition and schedule the processing tasks according to given optimization functions such as data throughput, memory usage, energy consumption. Implementations based on dataflow programming approaches are recognized to be particularly interesting for this challenge, because dataflow network components can be partitioned onto the processing units always yielding correct system behaviors. Moreover, the space of feasible configurations can be explored using heuristics and this is not the case for other implementation approaches for which, for each configuration, it is required to rewrite entire parts of the application programs. This paper investigates the features of the design space exploration problem by considering a new formal formulation of the partitioning, scheduling and buffer dimensioning problem for the case of dynamic dataflow programs. Furthermore, it demonstrates which heuristics, with the associated optimization functions relying on this formulation, can be identified for providing high quality solutions.