Subthreshold Logic for Low-Area and Energy Efficient True Random Number Generator

This paper discusses the advantages of subthreshold logic for True Random Number Generators (TRNG). In this work, the entropy is modeled, and a lower bound of Shannon's entropy per output bit can quickly be estimated. Thanks to this model, sizing TRNGs in subthreshold logic is quite simple and defining design guidelines for low-energy and low-area TRNGs is straightforward. A TRNG in 180nm CMOS technology has been designed, demonstrating low complexity (305 gates) and energy efficacy (30pJ/bit) at 0.5 Kbit/s.