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Bridging the Latency Gap between NVM and DRAM for Latency-bound Operations

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Bridging the Latency Gap between NVM and DRAM for Latency-bound Operations

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An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance I-caches

Reducing set-associative cache energy via way-prediction and selective direct-mapping

Cache-Conscious Structure Layout

Using Generational Garbage Collection to Implement Cache-Conscious Data Placement

Reducing set-associative cache energy via way-prediction and selective direct-mapping

An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance I-caches

Using Generational Garbage Collection to Implement Cache-Conscious Data Placement

Cache-Conscious Structure Layout