A Dynamically Reconfigurable Platform for High-Performance and Low-Power On-Board Processing

FPGAs (Field Programmable Gate Array) are an attractive technology for high-speed data processing in space missions due to their unbeatable flexibility and best performance-to-power ratio in comparison to software. However FPGAs suffer from 3 major drawbacks: (1) higher programming effort is required with respect to software; (2) hardware resources need to be allocated for each implemented function in contrast to software functions which can be executed on the same processing hardware; and (3) FPGAs are required to adopt radiation hardening techniques when deployed in a space environment. This paper presents a reconfigurable platform that demonstrates how modern FPGAs can be considered as computing resources like any other, suitable for emerging spatial applications and not subjected to the above-mentioned drawbacks. In particular, we show that large FPGAs can be split in different regions containing concurrently-running accelerators which can support the execution of a single or multiple applications. Then, in the same way as software-based multiprogrammed and multithreaded systems can dynamically create, schedule and execute threads, FPGA-based accelerators can be swapped in and out according to scheduling needs by exploiting their dynamic partial reconfiguration capability. A proof of concept cloud detection algorithm for Sentinel-2 multispectral images has been implemented and tested on our platform to validate the system's design principles and performance.

Snap-On User-Space Manager for Dynamically Reconfigurable System-on-Chips

Andrea Guerrieri, Paolo Ienne, Sahand Kashani-Akhavan

Due to increased embedded processing requirements, modern SoCs are becoming heterogeneous computing platforms by combining traditional processing units with custom reconfigurable hardware accelerators (HAs) on an FPGA fabric. However, efficiently managing such HAs in an embedded Linux environment involves handling Linux kernel source code and creating custom device drivers specific to a target platform, therefore negatively impacting development costs, portability and time-to-market. To address this issue, we present LEOSoC, a snap-on user-space manager for dynamically reconfigurable SoCs. Using LEOSoC does not require any specific version of the Linux kernel, nor to rebuild a custom driver for each new kernel release.LEOSoC consists of a base hardware system and a software layer which run on SoCs from various vendors. The system identifies the SoC on which it is running and auto-adapts its communication channels to the HAs accordingly. Furthermore, LEOSoC allows applications to partially or completely change the structure of the HAs at runtime without rebooting the system by leveraging the underlying SoC support for dynamic full/partial FPGA reconfiguration. The system has been tested on multiple commercial off the shelf (COTS) boards from different vendors, each one running different versions of Linux, therefore proving the real portability and usability of LEOSoC in a custom industrial design. Finally, we use a cloud detection algorithm for multispectral image processing as a showcase for LEOSoC's capabilities and performance.

2019

Adding limited reconfigurability to superscalar processors

Marc Epalza

For the last thirty years, electronics, at first built with discrete components, and then as Integrated Circuits (IC), have brought diverse and lasting improvements to our quality of life. Examples might include digital calculators, automotive and airplane control assistance, almost all electrical household appliances, and the almost ubiquitous Personal Computer. Application-Specific Integrated Circuits (ASICs) were traditionally used for their high performance and low manufacturing cost, and were designed specifically for a single application with large volumes. But as lower product lifetimes and the pressures of fast marketing increased, ASICs' high design cost pushed for their replacement by Microprocessors. These processors, capable of implementing any functionality through a change in software, are thus often called General Purpose Processors. General purpose processors are used for everyday computing tasks, and found in all personal computers. They are also often used as building blocks for scientific supercomputers. Superscalar processors such as these require ever more processing power to run complex simulations, video games or versatile telecoms services. In the case of embedded applications, e.g. for portable devices, both performance and power consumption must be taken into account. In a bid to adapt a processor to some extent to select applications, fully reconfigurable logic can greatly improve the performance of a processor, since it is shaped for the best possible execution with the available resources. However, as reconfigurable logic is far slower than custom logic, this gain is possible only for some specific applications with large parallelism, after a detailed study of the algorithm. Even though this process can be automated, it still requires large computing resources, and cannot be performed at run time. To reduce the loss in speed compared to custom logic, it is possible to limit the reconfigurability to increase the breadth of applications where performance can be improved. However, as the application space increases, a careful analysis and design of the reconfigurability is required to minimize the speed loss, notably when dynamic reconfiguration is considered. As a case study, we analyze the feasibility of adding limited reconfigurability to the Floating Point Units (FPUs) of a general purpose processor. These rather large units execute all floating point operations, and may also be used for integer multiplication. If an application contains few or infrequent instructions that must be executed by the FPU, this idle hardware only increases power consumption without enhancing performance. This is often the case in non-scientific applications and even many recent and detailed video games which make heavy use of hardware display accelerators for 3D graphics. In a fast multiplier such as can be found in the FPU of a high performance processor, the logic to perform multiplication is a large tree of compressors to add all the partial products together. It is possible to add logic to allow the reconfiguration of part of this tree as several extra Arithmetic and Logic Units (ALU). This requires a detailed timing analysis for both the reconfigurable FPU and the extra ALUs, taking into account effects such as added wires and longer critical paths. Finally, the algorithm to decide when and how to reconfigure must be studied, in terms of eciency and complexity. The results of adding this limited reconfigurability to a mainstream superscalar processor over a large set of compute intensive benchmarks show gains of up to 56% in the best case, with an average gain of 11%. The application to an idealized huge top processor still shows slightly positive average gains, as the limits of available parallelism are reached, bounded by both the application and many of the characteristics of the processor. In all cases, binary compatibility is maintained, allowing the re-use of all existing software. We show that adding limited reconfigurability to a general purpose superscalar processor can produce interesting gains over a wide range of applications while maintaining binary compatibility, and without large modifications to the original design. Limited reconfigurability is worthwhile as it increases the design space, allowing gains to apply to a larger set of applications. These gains are achieved through careful study and optimization of the reconfigurable logic and the decision algorithm.

EPFL2004

Type-based event dissemination

Sébastien Bähni

With the explosion of broadband Internet connections in the late 80s, new types of applications, called distributed applications, came to light. These applications typically seek to provide a user with remote services that appear to that user as if they were local. For instance, when a user browses the Internet, web pages are downloaded from different servers and are displayed on the screen of the client's computer as if they were directly available on the computer itself. Typically one distinguishes two kinds of actors in such applications: clients, searching for information, and servers, providing the information. Furthermore, there are generally two models of interaction according to which these actors exchange information. In the first model, the client requests specific information and waits until the server replies to it. In the second model, the client registers its interests in some information with a set of servers and is notified when new information is available. Both models have their advantages and disadvantages but the second has obvious asynchrony benefits in a large-scale system in which it is very difficult to know the time taken to answer a request. The second model is usually encapsulated within the celebrated publish/subscribe abstraction. According to this abstraction, clients are either subscribers which express interest in specific information, or publishers which create and send pieces of information usually transmitted in the form of events (e.g., as HTML pages or plain data). The subscriber does not need to know a publisher or to be on-line with it to receive its published events. These properties are sometimes refer to as space and time decoupling respectively. Newsgroups are the most well known example of publish/subscribe system. While indeed appealing, the publish/subscribe abstraction is not easy to implement effectively. There are at least two challenging issues: (1) the representation of the events and (2) their dissemination on a large-scale or in a mobile environment. Events are usually transferred as XML messages or byte arrays. The system must therefore transform events into pieces of software implemented in its underlying language (e.g., Java, C#) before handling them. In addition, the reliable dissemination on a large-scale or in a mobile environment is not trivial, especially as in practice it is necessary to minimize the number of duplicates and parasite events (i.e., events of no interest) to save bandwidth and processing power. We focus in this thesis on devising and implementing algorithms which address the above two issues in publish/subscribe systems implemented in object-oriented languages (e.g., Java, C#) and such that the events that are transferred between the different actors correspond to serialized objects. These systems are also called type-based publish/subscribe systems. We first present techniques to detect events of interest and throw away parasite events. We show that these techniques are of major use for reliably disseminating events either on a large-scale or in a mobile environment without flooding the network. Finally, we illustrate type interoperable rules that let instances of two different types, but still representing the same entity, to be used indistinguishably. Together with the algorithms, we exhibit implementation prototypes and performance measures conducted over them.