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Data Structures and Algorithms for Logic Synthesis in Advanced Technologies

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Magnonics is a young field of research and technology emerging at the interfaces between the study of spin dynamics, on the one hand, and a number of other fields of nanoscale science and technology, on the other. We review the foundations and recent achie ...

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During many decades, Moore's law, which predicts an exponential increase in performance of semiconductor logic circuits and memories and an exponential decrease in their area, has proven its universal validity. It also helped the semiconductor industry pre ...

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Arithmetic Optimization for Custom Instruction Set Synthesis

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One of the ways that custom instruction set extensions can improve over software execution is through the use of hardware structures that have been optimized at the arithmetic level. Arithmetic hardware, in many cases, can be partitioned into networks of f ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

Challenges in Automatic Optimization of Arithmetic Circuits

Paolo Ienne, Philip Brisk, Ajay Kumar Verma

Despite the impressive progress of logic synthesis in the past decade, finding the best architecture for a given circuit still remains an open and largely unsolved problem, especially for arithmetic circuits. In many cases, the outcome of even the most adv ...

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Design of Compact Imperfection-Immune CNFET Layouts for Standard-Cell-Based Logic Synthesis

Giovanni De Micheli, David Atienza Alonso, Shashi Kanth Bobba, Jie Zhang

The quest for technologies with superior device characteristics has showcased Carbon Nanotube Field Effect Transistors (CNFETs) into limelight. Among the several design aspects necessary for today’s grail in CNFET technology, achieving functional immunity ...

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This paper exploits the unique in-ﬁeld controllability of the device polarity of ambipolar carbon nanotube ﬁeld effect transistors (CNTFETs) to design a technology library with higher expressive power than conventional CMOS libraries. Based on generalized ...

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Approximate BDD Minimization by Weighted A*

Reduced ordered Binary Decision Diagrams (BDDs) are a data structure for efficient representation and manipulation of Boolean functions. They are frequently used in logic synthesis. The size of BDDs depends on a chosen variable ordering, i.e. the size may ...

Institute of Electrical and Electronics Engineers2009

Variable latency speculative addition: A new paradigm for arithmetic circuit design

Paolo Ienne, Philip Brisk, Ajay Kumar Verma

Adders are one of the key components in arithmetic circuits. Enhancing their performance can significantly improve the quality of arithmetic designs. This is the reason why the theoretical lower bounds on the delay and area of an adder have been analysed, ...

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Compositional verification for component-based systems and application

Joseph Sifakis

We present a compositional method for the verification of component-based systems described in a subset of the BIP language encompassing multi-party interaction without data transfer. The method is based on the use of two kinds of invariants. Component inv ...

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Structured analog CMOS design based on the device inversion level

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