Low-Latency High-Bandwidth Circuit and System Design for Trigger Systems in High Energy Physics
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In the scope of the development of a complete top-down design flow targeting clock and data recovery circuits for high-speed data links, we present two methods to analyze the jitter tolerance of such links, based on statistical simulation of incoming data ...
In this paper we present an approach to rapid prototyping of advanced signal processing techniques for future wireless applications currently being adopted within Bell Labs Research. The aim of the "Bell Labs Algorithm Development and Evaluation " (BLADE) ...
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Field programmable gate arrays (FPGA) are a recently developed family of programmable circuits. Like mask programmable gate arrays (MPGA), FPGAs implement thousands of logic gates. But, unlike MPGAs, a user can program an FPGA design as traditional program ...
Architectural ornament, the art of decorative patterning, is commonly perceived as an historical characteristic for architecture which declined in the beginning of the 20th century. The lecture of Adolf Loos in 1908 “Ornament and Crime” [1] can certainly b ...
TU Wien / Springer / Österreichischer Kunst- und Kulturverlag2005
A few years ago, a perceptually-tuned grayscale character generation technique was developed in order to automatically synthesize grayscale characters looking like manually-tuned pixmap characters. Weight and contrast controlled grayscale characters are ob ...
On-chip wires are becoming unreliable as the effect of various noise sources increases with technology scaling. This leads to unpredictable timing delay variations on the interconnect wires. There is a significant need to mitigate the effect of parasitics ...
Future Systems on Chips (SoCs) will integrate a large number of processor and storage cores onto a single chip and require Networks on Chip (NoC) to support the heavy communication demands of the system. The individual components of the SoCs will be hetero ...
A novel design-for-test (DFT) method that requires minor modifications to the controller in the register-transfer level (RTL) description of a circuit is presented. The control/data flow graph representation of an RTL circuit is used for analysing the test ...