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GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI

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GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI

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Inexact-Aware Architecture Design for Ultra-Low Power Bio-Signal Analysis

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement

Tunnel Field Effect Transistors

Investigation of Tunnel Field-Effect Transistors as a Capacitor-less Memory Cell

Design of Digital SoC for Operation at High Temperatures

1T Capacitor-less DRAM cell based on asymmetric Tunnel FET design

Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology

Variability-Aware Design Space Exploration of Embedded Memories

4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes

Single event upset mitigation in low power SRAM design