Reinforcement Learning-Based Joint Reliability and Performance Optimization for Hybrid-Cache Computing Servers

Computing servers play a key role in the development and process of emerging compute-intensive applications in recent years. However, they need to operate efficiently from an energy perspective viewpoint, while maximizing the performance and lifetime of the hottest server components (i.e., cores and cache). Previous methods focused on either improving energy efficiency by adopting new hybrid-cache architectures including the resistive random-access memory (RRAM) and static random-access memory (SRAM) at the hardware level, or exploring trade-offs between lifetime limitation and performance of multi-core processors under stable workloads conditions. Therefore, no work has so far proposed a co-optimization method with hybrid-cache-based server architectures for real-life dynamic scenarios taking into account scalability, performance, lifetime reliability, and energy efficiency at the same time. In this paper, we first formulate a reliability model for the hybrid-cache architecture to enable precise lifetime reliability management and energy efficiency optimization. We also include the performance and energy overheads of cache switching, and optimize the benefits of hybrid-cache usage for better energy efficiency and performance. Then, we propose a runtime Q-Learning-based reliability management and performance optimization approach for multi-core microprocessors with the hybrid-cache architecture, jointly incorporated with a dynamic preemptive priority queue management method to improve the overall tasks' performance by targeting to respect their end time limits. Experimental results show that our proposed method achieves up to 44% average performance (i.e., tasks execution time) improvement, while maintaining the whole system design lifetime longer than 5 years, when compared to the latest state-of-the-art energy efficiency optimization and reliability management methods for computing servers.

Micro-architectural Analysis of Database Workloads

Utku Sirin

Database workloads have significantly evolved in the past twenty years. Traditional database systems that are mainly used to serve Online Transactional Processing (OLTP) workloads evolved into specialized database systems that are optimized for particular types of workloads. Data warehousing applications have led to Online Analytical Processing (OLAP) workloads and real-time analytical processing applications have led to Hybrid Transactional and Analytical Processing (HTAP) workloads. Similarly, modern hardware has significantly evolved in the past twenty years. Unicore, simple processors with megabytes of main memory have evolved into multi-core, power-limited processors with hundreds of gigabytes of main memory. Furthermore, the processors have complex micro-architectural features such as Single Instruction Multiple Data (SIMD) instructions and complex branch predictors. Advancements in processor technology have led to further evolution of database systems with novel system architectures and query processing paradigms. We present the micro-architectural behavior of modern database workloads on a modern processor for various categories of workloads and generations of database systems. We examine three main categories of database workloads and study them separately: OLTP, OLAP, and HTAP. We show that OLTP systems spend most of their execution time waiting for instruction-cache or data-cache misses, where the data-cache misses are due to the random data-accesses during the index lookup operation. While using an efficient index structure can significantly reduce the number of data-cache misses, the main micro-architectural bottleneck remains the data-cache misses due to the costly random data-accesses. Hence, OLTP systems should adopt techniques that mitigate the random data-accesses. OLAP systems spend most of their execution time in data-cache misses, where the data-cache misses are due to high pressure on the memory bandwidth for sequential-scan-heavy queries, and are due to random data-accesses for join-intensive queries. OLAP systems that follow tuple-at-a-time execution models efficiently use the CPU cycles. However, they require executing a significantly larger number of instructions hence are significantly slower than the systems that follow vector-at-a-time and compiled execution models. Therefore, OLAP systems should use efficient execution models and adopt techniques that mitigate data-cache misses. HTAP systems combine OLTP and OLAP systems into a single, unified system, where the OLTP and OLAP systems run on the same hardware and on the same data. Running on the same hardware results in hardware-level interference, where the OLTP throughput significantly drops due to the OLAP side sharing the hardware resources. Running on the same data results in increased OLAP query execution time due to the need for the OLAP side to process the fresh tuples generated by the OLTP side. Therefore, HTAP systems should adopt techniques that mitigate the hardware-level interference and should make sure that the OLAP side uses enough resources to minimize the increased query execution time.

EPFL2021

Hardware/Software Co-Design and Reliability Analysis of Ultra-Low Power Biomedical Devices

Soumya Subhra Basu

Smart health monitoring devices, known as Wireless Body Sensor Nodes (WBSN) are transforming today's health-care landscape, shifting it from traditional hospital-based methods toward more personalized approaches. Their demand is ever-increasing in the modern world, where an overwhelming majority of deaths are caused by chronic cardiovascular diseases. WBSNs provide low-cost, unobtrusive and wearable solutions for continuous health-monitoring. These small autonomous devices are capable of acquiring, processing and wirelessly transmitting biological signals to medical personnel, typically relying on a limited on-board power source. Since WBSNs are desired to operate over prolonged periods, producing potentially critical data, their reliability and energy efficiency are of paramount importance. State-of-the-Art (SoA) WBSNs are able to process on-board the sensed bio-signals, like Electrocardiograms (ECG), transmitting only compact sets of clinically-relevant features instead of the entire acquired signal. This scenario moves the energy bottleneck of such devices from the transmission link to the computation-intensive Bio-Signal Processing (BSP) segment. To improve their energy efficiency, in this thesis, I propose strategies ranging from architectural to technology levels. First, I explore the applicability of a relaxed-reliability computing paradigm resulting from ultra-low voltage operations. I begin by modeling memory failures ensuing from voltage over-scaling and fabrication variability-related issues, studying their effects at the application level. To this end, I introduce novel data significance-based protection approaches for countering failures in embedded memories, showcasing up to 20% reduction in the energy budget compared to existing solutions. In addition, I devise lightweight hardware- and software-level error monitoring solutions that cope with memory failures, when unprotected. Experimental results demonstrate that these strategies ensure minimal performance degradation, achieving up to 24% energy savings with respect to the SoA. In the second part of the thesis, I employ novel approaches featuring heterogeneous WBSNs with a reconfigurable accelerator and emerging memory technologies. I commence by performing a study to identify the computationally intensive segments of BSP algorithms that can potentially be accelerated on a reconfigurable fabric. I adopt a top-down approach to do so, extracting kernels from the high-level application code, eventually optimizing and mapping them for execution on a time- and resource-shared Coarse Grain Reconfigurable Array (CGRA). I prove the effectiveness of the proposed platform by exhibiting up to 11x performance improvement and 37% energy savings over the SoA. Then, I combine relaxed-reliability computation and CGRA-based WBSNs, with my experiments exhibiting as much as 70% reduction in energy consumption compared to the current SoA, while assuring safe system operation. I conclude this work by exploring the integration of emerging Resistive Random Access Memory (ReRAM) technologies to traditional WBSN platforms, aimed at reducing their ever-increasing leakage energy consumption. In this regard, I report the memory-level endurance challenges faced due to aging and propose lightweight solutions for prolonged device usage. Obtained results highlight up to 65% increase in energy efficiency with respect to the SoA, including the overheads required for extended device functionality.

EPFL2019

Exploiting Compute Caches for Memory Bound Vector Operations

Gabriel Falcao Paiva Fernandes, Paolo Ienne, João Miguel Morgado Pereira Vieira

To reduce the average memory access time, most current processors make use of a multilevel cache subsystem. However, despite the proven benefits of such cache structures in the resulting throughput, conventional operations such as copy, simple maps and reductions still require moving large amounts of data to the processing cores. This imposes significant energy and performance overheads, with most of the execution time being spent moving data across the memory hierarchy. To mitigate this problem, a Cache Compute System (CCS) that targets memory-bound kernels such as map and reduce operations is proposed. The developed CCS takes advantage of long cache lines and data locality to avoid data transfers to the processor and exploits the intrinsic parallelism of vector compute units to accelerate a set of 48 operations commonly used in map and reduce patterns. The CCS was validated by integrating it with an MB-Lite soft-core in a Xilinx Virtex-7 VC709 Development Board. When compared to the MB-Lite core, the proposed CCS presents performance improvements in the execution of the commands ranging from 4x to 408x, and energy efficiency gains from 6x to 328x.