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27.3 Area-efficient 1GS/s 6b SAR ADC with charge-injection-cell-based DAC

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27.3 Area-efficient 1GS/s 6b SAR ADC with charge-injection-cell-based DAC

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High-Speed Wireline Link Design

Implementation of Low-Power 6–8 b 30–90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS

Toward direct light-to-digital conversion using a pulse-driven hybrid MOS-PN photodetector

Energy-Efficient High-Speed SAR ADCs in CMOS

Distributed average consensus with quantization refinement

On-Chip Digital Background Calibration of Pipelined Analog-to-Digital Converters using Digital Assistance to support Nonlinear Residue Amplification

A 14b extended counting ADC implemented in a 24Mpixel APS-C CMOS image sensor

Design and Exploration of Low-Power Analog to Information Conversion Based on Compressed Sensing

An Algorithm to Compensate the Effects of Spurious PLL Tones in Spectrum Sensing Architectures

Clock Jitter Compensation in High-Rate ADC Circuits