A Noise Reconfigurable All-Digital Phase-Locked Loop Using a Switched Capacitor-Based Frequency-Locked Loop and a Noise Detector
Related publications (125)
Graph Chatbot
Chat with Graph Search
Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.
DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.
The noise emission level from a vehicle is significantly influenced by different driving conditions and drivers’ behaviour. Almost all the in practice road traffic noise estimation models do not differentiate between different operating conditions. In this ...
After years of intensive research effort, the design of RF integrated circuits in CMOS has now reached a wide acceptance for industrial designs. This is due to the high unity gain frequency and low-noise performance of today's deep sub micrometer MOS trans ...
This paper focuses on practical aspects when performing boresight calibration in airborne laser scanning using rigorous methodology implemented in LIBOR software. LIBOR technique, introduced by (Skaloud and Lichti, 2006), is based on expressing the boresig ...
A compact carrier generation system enabling proper interoperability among quad-band GSM, WCDMA (FDD and TDD) and WLAN (802.11a/b/g) standard is developed. The implementation is achieved in 0.25μm BiCMOS-SiGe process. The measured tuning range is higher th ...
this paper describes a phase-locked loop (PLL) designed for clock multiplication in a LVDS transmitter. The PLL consists of a novel low-jitter charge-pump, a fully differential ring-oscillator based VCO, a dynamic-logic PFD, a 2nd order passive loop filter ...
A novel charge pulse detection circuit is presented, consisting of a continuous reset resistor in series with the charge pulse generator, followed by a simple amplifier and pulse shaping circuit. Realization with a 0.18 μm CMOS process (UMC) will result in ...
A compact carrier generation system enabling proper interoperability among quad-band GSM, WCDMA (FDD and TDD), and WLAN (802.11a/b/g) standards is developed. The implementation is achieved in 0.25-mum BiCMOS-SiGe process. The measured tuning range is highe ...
The recent advances made in MEMS and particularly in RF MEMS technology are enabling new architectures for the integration of RF transceivers with improved performance and smaller size. Several fundamental building blocks benefit from the availability of h ...
A negative-feedback scheme is applied to the gain stage of RC and LC ring oscillators to extend the frequency tuning range and to enhance the maximum oscillation frequency, respectively. This can be achieved without penalties in power consumption, supply v ...
As RF IC design has become more prevalent and more demanding, the need for a more precise VCO phase noise model has arisen. For both MOS and bipolar VCO's new formulas are still being proposed to model the phase noise, which is a key factor for a precise o ...