Reference Oversampling PLL Achieving −256-dB FoM and −78-dBc Reference Spur
Related publications (49)
Graph Chatbot
Chat with Graph Search
Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.
DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.
Les effets de la vibration musculaire peuvent généralement persister après la fin de la stimulation. L’extinction de ce post-effet fut étudié durant la marche humaine. Six sujets ont réalisé une tâche locomotrice (six pas successifs) en condition témoin, e ...
This paper presents a continuous voltage and frequency scaling approach achieving lower transition (both energy and time) overheads implied by changing voltage levels, at a very low power dissipation and silicon area cost for multi-processor systems with i ...
A compact carrier generation system enabling proper interoperability among quad-band GSM, WCDMA (FDD and TDD), and WLAN (802.11a/b/g) standards is developed. The implementation is achieved in 0.25-mum BiCMOS-SiGe process. The measured tuning range is highe ...
In this paper, a solution to realize local oscillators (LO) for a low power super-heterodyne receiver is presented. The first oscillator uses a bulk acoustic wave (BAW) resonator with high Q-factor. A quasi- harmonic quadrature relaxation oscillator with l ...
As RF IC design has become more prevalent and more demanding, the need for a more precise VCO phase noise model has arisen. For both MOS and bipolar VCO's new formulas are still being proposed to model the phase noise, which is a key factor for a precise o ...
A method and apparatus for a fast and automatic setting of the phase locked loop (PLL) output frequency that significantly improves linearity, locking range as well as spectrum purity, jitter and phase noise performances is disclosed. I n one embodiment, a ...
This paper presents a continuous voltage and frequency scaling approach achieving lower transition (both energy and time) overheads implied by changing voltage levels, at a very low power dissipation and silicon area cost for multi-processor systems with i ...
The recent advances made in MEMS and particularly in RF MEMS technology are enabling new architectures for the integration of RF transceivers with improved performance and smaller size. Several fundamental building blocks benefit from the availability of h ...
this paper describes a phase-locked loop (PLL) designed for clock multiplication in a LVDS transmitter. The PLL consists of a novel low-jitter charge-pump, a fully differential ring-oscillator based VCO, a dynamic-logic PFD, a 2nd order passive loop filter ...