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Stable Al 2 O 3 Encapsulation of MoS 2 ‐FETs Enabled by CVD Grown h‐BN

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A High-PDE, Backside-Illuminated SPAD in 65/40-nm 3D IC CMOS Pixel With Cascoded Passive Quenching and Active Recharge

Edoardo Charbon, Scott Anthony Lindner, Martin Wolf

We present a complete pixel based on a single-photon avalanche diode (SPAD) fabricated in a backside-illuminated (BSI) 3D IC technology. The chip stack comprises an image sensing tier produced in a 65-nm image sensor technology and a data processing tier i ...

2017

Multiple-Independent-Gate Field-Effect Transistors for High Computational Density and Low Power Consumption

Jian Zhang

Transistors are the fundamental elements in Integrated Circuits (IC). The development of transistors significantly improves the circuit performance. Numerous technology innovations have been adopted to maintain the continuous scaling down of transistors. W ...

EPFL2016

Contact resistance effects in organic n-channel thin-film transistors

Reinhold Rödel

Organic thin-film transistors (TFTs) have undergone tremendous progress in the past few years. Their great potential in terms of mechanical flexibility, light weight, low-cost and large-area fabrication makes them promising candidates for novel electronic ...

EPFL2016

Charge-transport properties of monolayer MoS2 at the interface with dielectric materials

Simone Bertolazzi

Two-dimensional (2D) semiconductors, consisting of single-sheets of layered transition metal dichalcogenides (TMD), are attracting enormous interest from both fundamental science and technology. Monolayer molybdenum disulfide (MoS2), a typical example from ...

EPFL2015

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This work demonstrates the first fabricated 4-transistor logic gates using polarity-configurable, gate-all- around silicon nanowire transistors. This technology enhances conventional CMOS functionality by adding the degree of free- dom of dynamic polarity ...

Institute of Electrical and Electronics Engineers2014

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A 3D vertically stacked silicon nanowire (SiNW) and Fin field effect transistor (FET) featuring a high density array (7 or 8 x 20 SiNWs, > 4 Fins vertically stacked) of fully depleted, ultra-thin (SiNWs diameters similar to 15-30 nm, Fin width/height fw si ...

Elsevier2014

FinFET integrated low-power circuits for enhanced sensing applications

Mihai Adrian Ionescu, Antonios Bazigos, Alexandru Rusu, Sara Rigante, Paolo Livi

This work presents different circuit architectures that combine sensing and signal readout functions. The basic building block is a Fin Field-Effect Transistor (Fin-FET) used as both sensor and metal gate transistor. Moreover, a hybrid partially gated FinF ...

Elsevier2013

Single-layer MoS₂

Branimir Radisavljevic

This thesis explores the electronic properties of one layered transition-metal dichalcogenide – single-layer MoS2, and demonstrates the first transistors and integrated circuits with characteristics that outperform graphene electronics in many aspects and ...

EPFL2013

From All-Si Nanowire TFETs Towards III-V TFETs

Hesham Ghoneim

Performance improvement by device scaling has been the prevailing method in the semiconductor industry over the past four decades. However, current silicon transistor technology is approaching a fundamental limit where scaling does not improve device perfo ...

EPFL2012

Multi-gate Si nanowire MOSFETs

Mohammad Najmzadeh

Multi-gate devices e.g. gate-all-around (GAA) Si nanowires and FinFETs are promising can- didates for aggressive CMOS downscaling. Optimum subthreshold slope, immunity against short channel effect and optimized power consumption are the major benefits of s ...

EPFL2012