Exploring negative capacitance and neuromorphic devices based on CMOS-compatible ferroelectric HfO2

Ferroelectric materials are explored for numerous applications thanks to their properties associated with electrically switchable spontaneous polarization. Perovskites are an established class of ferroelectrics used for sensors and actuators. However, they present limitations if integrated into microelectronic since they are neither CMOS compatible nor easily scalable. The game-changing solution came from the new family of ferroelectric materials based on HfO2 that emerged within the last decade, which show integrability in scaled CMOS devices.HfO2-based ferroelectrics are considered a rising candidate for different applications, among which neuromorphic devices and negative capacitance (NC) logic switches. Neuromorphic devices rely on the gradual polarization switching capability, which can reproduce synaptic plasticity. By mimicking the analog operation of the human brain, neuromorphic computing is expected to be more energy-efficient than the digital Von Neumann architecture. On the other hand, in logic switches, hysteresis is usually avoided, and a steep subthreshold swing is desired. For this purpose, negative capacitance field-effect transistors (NC-FETs) show a strong promise of overcoming the thermionic Boltzmann constraint of 60 mV/dec and continuing CMOS scaling. NC-FETs rely on exploiting the NC region of the polarization-electric field curve predicted by the Landau-Ginzburg-Devonshire (LGD) model. This thesis aims to study the NC effect and its interplay with the polarization switching mechanisms of one of the best-known members of HfO2-based ferroelectrics, the Si-doped HfO2 (Si:HfO2), and then to integrate it onto electronic devices. Temperature-dependent switching in Si:HfO2 capacitors were studied, and the results were used to calibrate the LGD model, confirming the intrinsic switching mechanism experimentally. Then Si:HfO2 was integrated into gate stack transistors to verify its functionality. In this framework, two structures were studied, one with an inner metal gate (IG) between the insulator and ferroelectric and one without it. Thanks to nanosecond-range pulse measurement, the S-shaped curve, predicted by the LGD model, was extracted, and the NC region was observed. Following the previous study, the two gate stacks were implemented in a junctionless transistor (JLFET) platform with a Si channel of 12 nm, resulting in a device with Ion/Ioff of 6 orders of magnitude. The ferroelectric-JLFET (Fe-JLFET) without IG presented a hysteresis-free transfer characteristic and an improved subthreshold swing of 35% over 1.3 decades of drain current with pulse gate voltages compared to DC. On the contrary, the Fe-JLFET with IG showed a ferroelectric hysteretic behavior, and the Si:HfO2 gradual switching is exploited to mimic the synaptic plasticity. Additionally, the back-gate voltage biasing is used to tune the synaptic weight by more than 400x.Overall, this Ph.D. work confirms the potential of Fe-JLFET for both neuromorphic synapses and NC logic devices and highlights the requirements and limits of operation by studying how HfO2-based ferroelectric properties evolve from the capacitor to integration into the gate stack.

Ferroelectric transistors with improved characteristics at high temperature

Didier Bouvet, Mihai Adrian Ionescu, Livio Lattanzio, Giovanni Antonio Salvatore, Nava Setter, Igor Stolichnov

We report on the temperature dependence of ferroelectric metal-oxide-semiconductor (MOS) transistors and explain the observed improved characteristics based on the dielectric response of ferroelectric materials close to the Curie temperature. The hysteretic current-voltage static characteristics of a fully depleted silicon-on-insulator transistor, with 40 nm vinylidene fluoride trifluorethylene, and 10 nm SiO2 gate stack, are measured from 300 to 400 K. In contrast with conventional MOS field effect transistors (MOSFETs), the subthreshold swing and the transconductance show, respectively, a minimum and a maximum near the Curie temperature (355 K) of the ferroelectric material. A phenomenological model is proposed based on the Landau-Ginzburg theory. This work demonstrates that a MOSFET with a ferroelectric layer integrated in the gate stack could have nondegraded or even improved subthreshold swing and transconductance at high temperature even though the hysteresis window is reduced. As a consequence, we suggest that for ferroelectric transistors with appropriately designed Curie temperatures, the performance degradation of logic or analog circuits, nowadays operating near 100 degrees C, could be avoided. (C) 2010 American Institute of Physics. [doi: 10.1063/1.3467471]

American Institute of Physics2010

Negative Capacitance as Performance Booster for Tunnel FETs and MOSFETs: An Experimental Study

Francesco Bellando, Christian Enz, Mihai Adrian Ionescu, Farzan Jazaeri, Ali Saeidi, Igor Stolichnov

This letter reports for the first time a full experimental study of performance boosting of tunnel FETs (TFETs) and MOSFETs by negative capacitance (NC) effect. We discuss the importance of capacitance matching between a ferroelectric NC and a device capacitance to achieve hysteretic and non-hysteretic characteristics. PZT ferroelectric capacitors are connected to the gate of three terminals TFETs and MOSFETs and partial or full matching NC conditions for amplification and stability are obtained. First, we demonstrate the characteristics of hysteretic and non-hysteretic NC-TFETs. The main performance boosting is obtained for the non-hysteretic NC-TFET, where the ON-current is increased by a factor of 500 times, transconductance is enhanced by three orders of magnitude, and the low slope region is extended. The boosting of performance is moderate in the hysteretic NC-TFET. Second, we investigate the impact of the same NC booster on MOSFETs. Subthreshold swing as steep as 4 mV/decade with a 1.5-V hysteresis is obtained on a commercial device fabricated in 28-nm CMOS technology. Moreover, we demonstrate a nonhysteretic NC-MOSFET with a full matching of capacitances and a reduced subthreshold swing down to 20 mV/decade

2017