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Design and analysis of a systolic array for neural computation

Related publications (270)

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Power Efficient Hardware Implementation of a Fuzzy Neural Network

Rafal Tomasz Dlugosz

This paper presents a digital, transistor level implemented neo-fuzzy neural network. This type of neural network is particularly well suited for real-time applications like those encountered in signal processing and nonlinear system identification. We con ...

Technical University of Lodz2010

Scalable instruction set simulator for thousand-core architectures running on GPGPUs

David Atienza Alonso, Luca Benini, Martino Ruggiero, Shivani Raghav

Simulators are still the primary tools for development and performance evaluation of applications running on massively parallel architectures. However, current virtual platforms are not able to tackle the complexity issues introduced by 1000-core future sc ...

IEEE Press2010

ParaLog: enabling and accelerating online parallel monitoring of multithreaded applications

Babak Falsafi, Evangelos Vlachos

Instruction-grain lifeguards monitor the events of a running application at the level of individual instructions in order to identify and help mitigate application bugs and security exploits. Because such lifeguards impose a 10-100X slowdown on existing pl ...

ACM Press2010

Reservoir optimization in recurrent neural networks using properties of Kronecker product

Martin Hasler, Ali Ajdari Rad, Mahdi Jalili

Recurrent neural networks based on reservoir computing are increasingly being used in many applications. Optimization of the topological structure of the reservoir and the internal connection weights for a given task is one of the most important problems i ...

2010

A Tighter Analysis of Work Stealing

Nicolas Gabriel Gast, Denis Trystram

Classical list scheduling is a very popular and efficient technique for scheduling jobs in parallel platforms. However, with the increasing number of processors, the cost for managing a single centralized list becomes prohibitive. The objective of this wor ...

Springer Berlin Heidelberg2010

System for generating computer processor

A method and apparatus to produce a net list of gates and Flip-Flops for one algorithm in order to find the best compromise between power consumption, speed and silicon surface by using a two step process. First the algorithm is written for a processor tha ...

2010

Reduction to Condensed Forms for Symmetric Eigenvalue Problems on Multi-core Architectures

Daniel Kressner

We investigate the performance of the routines in LAPACK and the Successive Band Reduction (SBR) toolbox for the reduction of a dense matrix to tridiagonal form, a crucial preprocessing stage in the solution of the symmetric eigenvalue problem, on general- ...

Springer, New York2010

Montgomery Multiplication on the Cell

Joppe Willem Bos, Marcelo Kaihara

A technique to speed up Montgomery multiplication targeted at the Synergistic Processor Elements (SPE) of the Cell Broadband Engine is proposed. The technique consists of splitting a number into four consecutive parts. These parts are placed one by one in ...

Springer-Verlag New York, Ms Ingrid Cunningham, 175 Fifth Ave, New York, Ny 10010 Usa2010

Genetic representation and evolvability of modular neural controllers

Dario Floreano, Claudio Mattiussi, Peter Dürr

The manual design of con- trol systems for robotic devices can be challenging. Methods for the automatic synthesis of control systems, such as the evolution of artificial neural networks, are thus widely used in the robotics community. However, in many rob ...

Institute of Electrical and Electronics Engineers2010

A hardware-software codesign framework for cellular computing

Pierre-André Mudry

Until recently, the ever-increasing demand of computing power has been met on one hand by increasing the operating frequency of processors and on the other hand by designing architectures capable of exploiting parallelism at the instruction level through h ...

EPFL2009