Associativity-agnostic in-cache computing memory architecture optimized for multiplication

A random access memory array including a plurality of local memory group ways, each local memory group way including, a plurality of local memory groups, each local memory group including, a memory column including a plurality of memory cells, a pair of local bitlines operatively connected to the plurality of memory cells, and a local group periphery including a local bitline multiplexer operatively connected with the pairs of local bitlines of the corresponding local memory group; and a pair of global read bitlines operatively connected to outputs of the plurality of local group peripheries, a global read bitline multiplexer operatively connected to outputs of the plurality of pairs of the global read bitlines from the local memory group ways, and a bitline operational block operatively connected an output of the global read bitline multiplexer.