Resource Sharing in Dataflow Circuits

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Pipeline Synthesis and Optimization from Branched Feedback Dataflow Programs

Marco Mattavelli, Simone Casale Brunet, Endri Bezati, Anatoly Prihozhy

Large dataflow designs are a result of behavioral specification of modern complex digital systems and/or a result of unfolding and transforming looped and branched programs. Since deep-submicron silicon technology provides large amounts of available resour ...

SPRINGER2020

Data Structures and Algorithms for Logic Synthesis in Advanced Technologies

Eleonora Testa

Logic synthesis is a key component of digital design and modern EDA tools; it is thus an essential instrument for the design of leading-edge chips and to push the limits of their performance. In the last decades, the electronic circuits community has evolv ...

EPFL2020

An Heterogeneous Compiler Of Dataflow Programs For Zynq Platforms

Marco Mattavelli, Simone Casale Brunet, Romuald Mosqueron, Endri Bezati

In recent years, the number and variety of heterogeneous multiprocessor system-on-chip MPSoCs, such as for instance Zynq platforms, has sensibly increased. However, today all design flow solutions capable of programming the different components of such pla ...

IEEE2019

SAT-Based Exact Synthesis for Multi-Level Logic Networks

Winston Jason Haaswijk

Today, the design of electronic systems is largely automated. The practice of using software automation technologies for the design of electronic hardware is commonly referred to as Electronic Design Automation (EDA). EDA comprises a large set of tools, fr ...

EPFL2019

Scaling Functional Synthesis and Repair

Emmanouil Koukoutos

Program synthesis was first proposed a few decades ago, but in the last decade it has gained increased momentum in the research community. The increasing complexity of software has dictated the urgent need for improved supporting tools that verify the soft ...

EPFL2019

Composite Data Types in Dynamic Dataflow Languages as Copyless Memory Sharing Mechanism

Marco Mattavelli, Endri Bezati, Aurélien François Gilbert Bloch

This paper presents new optimization approaches aiming at reducing the impact of memory accesses on the performance of dataflow programs. The approach is based on introducing a high level management of composite data types in dynamic dataflow programming l ...

2019

Experimental Generation and Time Multiplexing of Data-Carrying Nyquist Sinc Shaped Channels from a Single Microresonator-based Kerr Frequency Comb

Tobias Kippenberg, Maxim Karpov, Martin Hubert Peter Pfeiffer, Arne Kordts, Yiming Cao, Fatemeh Alishahi, Ahmad Fallahpour

We experimentally achieve optical time multiplexing of multiple Nyquist channels. A single microresonator Kerr comb allows the generation of multiple Nyquist sinc shaped pulse trains. TDM of pulse trains are obtained through wavelength conversion inside a ...

IEEE2019

Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs

Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Atri Bhattacharyya

When applications have unpredictable memory accesses or irregular control flow, dataflow circuits overcome the limitations of statically scheduled high-level synthesis (HLS). If memory dependences cannot be determined at compile time, dataflow circuits rel ...

IEEE COMPUTER SOC2019

Hardware Acceleration of HDR-Image Tone Mapping on an FPGA-CPU Platform Through High-Level Synthesis

Christian Enz, Vincent Frédéric Camus, Alessandro Pezzotta, Jérémy Lucien Maurice Schlachter, Mattia Cacciotti

In this paper, the hardware acceleration of a tone-mapping algorithm for High-Dynamic-Range image processing is presented. Starting from the C++ source code, High-Level Synthesis has been performed using Xilinx SDSoC for a Xilinx Zynq SoC device. After an ...

IEEE2018

Efficient Dynamic Optimisation Heuristics for Dataflow Pipelines

Marco Mattavelli, Simone Casale Brunet, Endri Bezati, Anatoly Prihozhy

Large dataflow designs appear as a result of functional specification of modern complex digital systems and/ or a result of unfolding and behavioral transformation of looped and branched programs. Since deep-submicron silicon technology provides large amou ...

IEEE2018

Page 3 of 4

SAT-Based Exact Synthesis for Multi-Level Logic Networks

Winston Jason Haaswijk

EPFL2019

Experimental Generation and Time Multiplexing of Data-Carrying Nyquist Sinc Shaped Channels from a Single Microresonator-based Kerr Frequency Comb

Tobias Kippenberg, Maxim Karpov, Martin Hubert Peter Pfeiffer, Arne Kordts, Yiming Cao, Fatemeh Alishahi, Ahmad Fallahpour

IEEE2019