Impact of Data Serialization over TSVs on Routing Congestion in 3D-Stacked Multi-Core Processors

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Realization and Control of Bulk and Surface Modes in 3D Nanomagnonic Networks by Additive Manufacturing of Ferromagnets

Dirk Grundler, Mohammad Hamdi, Mingran Xu, Huixin Guo, Axel Johan Marie Deenen

The high-density integration in information technology fuels the research on functional 3D nanodevices. Particularly ferromagnets promise multifunctional 3D devices for nonvolatile data storage, high-speed data processing, and non-charge-based logic operat ...

Wiley2023

Programmable frequency-bin quantum states in a nano-engineered silicon device

Matteo Galli, Marco Clementi

Frequency-bin qubits get the best of time-bin and dual-rail encodings, but require external modulators and pulse shapers to build arbitrary states. Here, instead, the authors work directly on-chip by controlling the interference of biphoton amplitudes gene ...

Nature Portfolio2023

Thermal and Voltage-Aware Performance Management of 3D MPSoCs with Flow Cell Arrays and Integrated SC Converters

David Atienza Alonso, Marina Zapater Sancho, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, Halima Najibi

Flow cell arrays (FCAs) concurrently provide efficient on-chip liquid cooling and electrochemical power generation. This technology is especially promising for three-dimensional multi-processor systems-on-chip (3D MPSoCs) realized in deeply scaled technolo ...

2022

Full System Exploration of On-Chip Wireless Communication on Many-Core Architectures

David Atienza Alonso, Marina Zapater Sancho, Giovanni Ansaloni, Rafael Medina Morillas, Yasir Mahmood Qureshi, Joshua Alexander Harrison Klein

In order to develop sustainable and more powerful information technology (IT) infrastructures, the challenges posed by the "memory wall" are critical for the design of high-performance and high-efficiency many-core computing systems. In this context, recen ...

IEEE2022

Thermal and Power-Aware Run-Time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays

David Atienza Alonso, Giovanni Ansaloni, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, Halima Najibi

Flow Cell Arrays (FCA) technology employs microchannels filled with an electrolytic fluid to concurrently provide cooling and power generation to integrated circuits (ICs). This solution is particularly appealing for Three-Dimensional Multi-Processor Syste ...

2022

Design and management of three-dimensional multi-processor systems-on-chip with integrated flow cell arrays

Halima Najibi

Three-Dimensional Multi-Processor Systems-on-Chip (3D MPSoCs) are promising solutions for highly intensive Artificial Intelligence (AI) and Big Data applications. They combine remarkably dense computation capabilities and massive communication bandwidths. ...

EPFL2022

DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks

Mirjana Stojilovic, Dina Gamaleldin Ahmed Shawky Mahmoud, David Dervishi

Field-programmable gate arrays (FPGAs) combine hardware reconfigurability with a high degree of parallelism. Consequently, FPGAs offer performance gains and power savings for many applications. A recent trend has been to leverage the hardware versatility o ...

2022

Piezoelectric suspended microchannel resonators

Damien Maillard

The objective of this PhD thesis is the development of a microfluidic platform for the real-time measurements of the mechanical properties of biological analytes at the single entity level. The systems developed for these purposes consist of piezoelectrica ...

EPFL2022

Development of a large-area, light-weight module using the MALTA monolithic pixel detector

Edoardo Charbon, Francesco Piro, Ashish Sharma

The MALTA pixel chip is a 2 cm x 2 cm large monolithic pixel detector developed in the Tower 180 nm imaging process. The chip contains four CMOS transceiver blocks at its sides which allow chip-to-chip data transfer. The power pads are located mainly at th ...

ELSEVIER2022

MALTA3: Concepts for a new radiation tolerant sensor in the TowerJazz 180 nm technology

Francesco Piro

The upgrade of the MALTA DMAPS designed in Tower 180 nm CMOS Imaging process will implement the numerous modifications, as well as front-end changes in order to boost the charge collection efficiency after the targeted fluence of 1x10(15) 1 MeVn(eq)/cm(2). ...

ELSEVIER2022

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