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Resource Sharing in Dataflow Circuits

Related publications (31)

A programmable low-power ADC interface for an ISFET sweat sensor used in a wearable multi-sensing system

Maher Kayal, Evgenia Voulgari, François Krummenacher

An application specific integrated circuit (ASIC) named ANTIGONE (ANalog To dIGital cONvErter) was designed in AMS 0.35 mu m technology to interface with four Ion-sensitive field-effect transistor (ISFET) sensors and perform real-time monitoring of some bi ...

IEEE2019

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A programmable low-power ADC interface for an ISFET sweat sensor used in a wearable multi-sensing system

Maher Kayal, Evgenia Voulgari, François Krummenacher

IEEE2019

Efficient Dynamic Optimisation Heuristics for Dataflow Pipelines

Marco Mattavelli, Simone Casale Brunet, Endri Bezati, Anatoly Prihozhy

Large dataflow designs appear as a result of functional specification of modern complex digital systems and/ or a result of unfolding and behavioral transformation of looped and branched programs. Since deep-submicron silicon technology provides large amou ...

IEEE2018

A Time-Division Multiplexing Signaling Scheme for Low-Power Multi-Drop Memory Links

Yusuf Leblebici, Gain Kim, Kiarash Gharibdoust, Chen Cao

A time-division multiplexing (TDM) digital channel coding scheme for wireline multi-drop interfaces has been proposed. Shaping the TX spectrum to avoid channel frequency notches, the proposed digital TDM signaling reduces inter-symbol interference (ISI) an ...

2017

A Time-Division Multiplexing Signaling Scheme for Inter-Symbol/Channel Interference Reduction in Low-Power Multi-Drop Memory Links

Seyed Armin Tajalli, Yusuf Leblebici, Gain Kim, Kiarash Gharibdoust, Chen Cao

A time-division multiplexing (TDM) digital channel coding scheme with inter-symbol interference (ICI) reduction property for multi-drop memory interfaces has been proposed. Shaping the TX spectrum to avoid channel frequency notches, the proposed digital TD ...

Ieee-Inst Electrical Electronics Engineers Inc2017

Optimization Opportunities in RRAM-based FPGA Architectures

Giovanni De Micheli, Xifan Tang, Pierre-Emmanuel Julien Marc Gaillardon

Static Random Access Memory (SRAM)-based routing multiplexers, whatever structure is employed, share a common limitation: their area, delay and power increase linearly with the input size. This property results in most SRAM-based FPGA architectures ...

IEEE2017

Buffer dimensioning for throughput improvement of dynamic dataflow signal processing applications on multi-core platforms

Marco Mattavelli, Malgorzata Maria Michalska, Simone Casale Brunet, Endri Bezati

Executing a dataflow program on a parallel platform requires assigning to each buffer a given size so that correct program executions take place without introducing any deadlock. Furthermore, in the case of dynamic dataflow programs, specific buffer size a ...

2017

Systematic Design Space Exploration of Dynamic Dataflow Programs for Multi-core Platforms

Malgorzata Maria Michalska

The limitations of clock frequency and power dissipation of deep sub-micron CMOS technology have led to the development of massively parallel computing platforms. They consist of dozens or hundreds of processing units and offer a high degree of parallelism ...

EPFL2017

FPGAs for the Masses: Affordable Hardware Synthesis from Domain-Specific Languages

Nithin George

Field Programmable Gate Arrays (FPGAs) have the unique ability to be configured into application-specific architectures that are well suited to specific computing problems. This enables them to achieve performances and energy efficiencies that outclass oth ...

EPFL2016

Generating Configurable Hardware from Parallel Patterns

Christos Kozyrakis

In recent years the computing landscape has seen an increasing shift towards specialized accelerators. Field programmable gate arrays (FPGAs) are particularly promising for the implementation of these accelerators, as they offer significant performance and ...

Assoc Computing Machinery2016

Pattern-based fpga logic block and clustering algorithm

Giovanni De Micheli, Xifan Tang, Pierre-Emmanuel Julien Marc Gaillardon

A routing architecture for fast interconnections between Look-Up Tables (LUTs) in a group of Basic Logic Elements (BLEs), whereby a size of the group ranges from 1 to k+1, where k is the number of inputs of a LUT, and LUTs in the group are indexed from 1 t ...

2016

Page 3 of 4

Efficient Dynamic Optimisation Heuristics for Dataflow Pipelines

Marco Mattavelli, Simone Casale Brunet, Endri Bezati, Anatoly Prihozhy

IEEE2018

A Time-Division Multiplexing Signaling Scheme for Low-Power Multi-Drop Memory Links

Yusuf Leblebici, Gain Kim, Kiarash Gharibdoust, Chen Cao

2017

A Time-Division Multiplexing Signaling Scheme for Inter-Symbol/Channel Interference Reduction in Low-Power Multi-Drop Memory Links

Seyed Armin Tajalli, Yusuf Leblebici, Gain Kim, Kiarash Gharibdoust, Chen Cao

Ieee-Inst Electrical Electronics Engineers Inc2017

Optimization Opportunities in RRAM-based FPGA Architectures

Giovanni De Micheli, Xifan Tang, Pierre-Emmanuel Julien Marc Gaillardon

IEEE2017

Buffer dimensioning for throughput improvement of dynamic dataflow signal processing applications on multi-core platforms

Marco Mattavelli, Malgorzata Maria Michalska, Simone Casale Brunet, Endri Bezati

2017