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A Low-Power Programmable Dynamic Frequency Divider

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Christian Enz
2008

Abstract

In this paper, a solution to realize a low-power programmable frequency divider using dynamic logic is proposed. By cascading compact dual-modulus divider slice with recursive feedback mechanisms, any dividing ratio is easily implemented. A 5-stages 0.18 mum CMOS implementation demonstrates a power consumption factor as low as 235 nW/MHz under 1.2 V supply for high dividing ratios.

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https://infoscience.epfl.ch/entities/publication/fcd75626-7b5f-480e-acd8-a9c4aaf0ea01

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