Publications associées à Fonction NON

Regular Fabric Design with Ambipolar CNTFETs for FPGA and Structured ASIC Applications

Giovanni De Micheli, Mohamed Haykel Ben Jamaa, Michele De Marchi

In this paper, we propose for the first time the application of ambipolar CNTFETs with in-field controllable polarities to design regular fabrics with static logic. We exploit the high expressive power provided by complementary static logic built with ambi ...

2010

Realization of the Conscience Mechanism in CMOS Implementation of Winner-Takes-All Self-Organizing Neural Networks

Rafal Tomasz Dlugosz

This paper presents a complementary metal–oxide– semiconductor (CMOS) implementation of a conscience mechanism used to improve the effectiveness of learning in the winnertakes- all (WTA) artificial neural networks (ANNs) realized at the transistor level. T ...

Institute of Electrical and Electronics Engineers2010

The high-mobility bended n-channel silicon nanowire transistor

Mihai Adrian Ionescu, Didier Bouvet, Kirsten Emilie Moselund, Vincent Pott, Luca De Michielis, Mohammad Najmzadeh

This work demonstrates a method for incorporating strain in silicon nanowire gate-all-around (GAA) n-MOSFETs by oxidation-induced bending of the nanowire channel and reports on the resulting improvement in device performance. The variation in strain measur ...

Institute of Electrical and Electronics Engineers2010

An experimental investigation of the surface potential in ferroelectric P(VDF-TrFE) FETs

Mihai Adrian Ionescu, Giovanni Antonio Salvatore, Alexandru Rusu

In this paper we report the fabrication and detailed electrical characterization of a ferroelectric transistor (Fe-FET) aiming at the extraction of its physical threshold voltage. The investigated transistors are fabricated on doped bulk silicon with a gat ...

2010

Novel Library of Logic Gates with Ambipolar CNTFETs: Opportunities for Multi-Level Logic Synthesis

Giovanni De Micheli, Mohamed Haykel Ben Jamaa

This paper exploits the unique in-ﬁeld controllability of the device polarity of ambipolar carbon nanotube ﬁeld effect transistors (CNTFETs) to design a technology library with higher expressive power than conventional CMOS libraries. Based on generalized ...

2009

Topological Frustration in Graphene Nanoflakes: Magnetic Order and Spin Logic Devices

Oleg Yazyev, Efthimios Kaxiras, Sheng Meng

Magnetic order in graphene-related structures can arise from size effects or from topological frustration. We introduce a rigorous classification scheme for the types of finite graphene structures (nanoflakes) which lead to large net spin or to antiferroma ...

2009

Arithmetic Optimization for Custom Instruction Set Synthesis

Paolo Ienne, Philip Brisk, Ajay Kumar Verma, Yi Zhu

One of the ways that custom instruction set extensions can improve over software execution is through the use of hardware structures that have been optimized at the arithmetic level. Arithmetic hardware, in many cases, can be partitioned into networks of f ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

Leakage Current Reduction Using Subthreshold Source-Coupled Logic

Seyed Armin Tajalli, Yusuf Leblebici

The performance of subthreshold source-coupled logic (STSCL) circuits for ultra-low power applications is explored. It is shown that the power consumption of STSCL circuits can be reduced well below the subthreshold leakage current of static CMOS circuits. ...

2009

Optimization of Nanoelectronic Systems Reliability under Massive Defect Density Using Distributed R-Fold Modular Redundancy

Alexandre Schmid, Yusuf Leblebici, Milos Stanisavljevic

The theoretical analysis of R-fold modular redundancy with distributed voters - distributed R-fold modular redundancy in terms of reliability is presented for the first time to the best of author's knowledge. This technique is compared in terms of resistan ...

IEEE Computer Soc Press, Customer Service Center, Po Box 3014, 10662 Los Vaqueros Circle, Los Alamitos, Ca 90720-1264 Usa2009

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Fonction NON

Regular Fabric Design with Ambipolar CNTFETs for FPGA and Structured ASIC Applications

Realization of the Conscience Mechanism in CMOS Implementation of Winner-Takes-All Self-Organizing Neural Networks

A novel ultra low-energy sub-threshold inverter based on nanoscale Field Effect Diode

The high-mobility bended n-channel silicon nanowire transistor

An experimental investigation of the surface potential in ferroelectric P(VDF-TrFE) FETs

Novel Library of Logic Gates with Ambipolar CNTFETs: Opportunities for Multi-Level Logic Synthesis

Topological Frustration in Graphene Nanoflakes: Magnetic Order and Spin Logic Devices

Arithmetic Optimization for Custom Instruction Set Synthesis

Leakage Current Reduction Using Subthreshold Source-Coupled Logic

Optimization of Nanoelectronic Systems Reliability under Massive Defect Density Using Distributed R-Fold Modular Redundancy

Graph Chatbot

Chattez avec Graph Search

Leakage Current Reduction Using Subthreshold Source-Coupled Logic

A novel ultra low-energy sub-threshold inverter based on nanoscale Field Effect Diode

The high-mobility bended n-channel silicon nanowire transistor

Novel Library of Logic Gates with Ambipolar CNTFETs: Opportunities for Multi-Level Logic Synthesis

Topological Frustration in Graphene Nanoflakes: Magnetic Order and Spin Logic Devices

Optimization of Nanoelectronic Systems Reliability under Massive Defect Density Using Distributed R-Fold Modular Redundancy

Realization of the Conscience Mechanism in CMOS Implementation of Winner-Takes-All Self-Organizing Neural Networks

Regular Fabric Design with Ambipolar CNTFETs for FPGA and Structured ASIC Applications

An experimental investigation of the surface potential in ferroelectric P(VDF-TrFE) FETs

Arithmetic Optimization for Custom Instruction Set Synthesis