Electronic circuit simulation

Résumé

Electronic circuit simulation uses mathematical models to replicate the behavior of an actual electronic device or circuit.
Simulation software allows for modeling of circuit operation and is an invaluable analysis tool. Due to its highly accurate modeling capability, many colleges and universities use this type of software for the teaching of electronics technician and electronics engineering programs. Electronics simulation software engages its users by integrating them into the learning experience. These kinds of interactions actively engage learners to analyze, synthesize, organize, and evaluate content and result in learners constructing their own knowledge. Simulating a circuit’s behavior before actually building it can greatly improve design efficiency by making faulty designs known as such, and providing insight into the behavior of electronics circuit designs. In particular, for integrated circuits, the tooling (photomasks) is expensive, breadboards are impractical, and

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Since the emergence of Silicon On Insulator (SOI) technology the research activities have been concentrated on a detailed analysis of SOI devices and their use in different application fields (low-voltage, low-power circuits, high temperature electronics, digital circuits, etc.). The present thesis deals with low-voltage, low-power mixed-mode design using a SOI technology. The goal is to establish the concepts that allow one to design SOI mixed-mode circuits, and to apply these concepts to the design of fully depleted (FD) and partially depleted (PD) SOI circuits and systems. Two studies have been realized in the scope of this work: a Hall sensor based microsystem design using an experimental FD SOI technology a DRAM design using capacitor-less 1T floating-body PD SOI memory cells. At the beginning of this thesis, two major types of SOI devices are introduced, namely FD and PD devices. The most important properties of these devices are then presented and compared to those of CMOS bulk devices. A design methodology based on design retargeting from bulk to SOI technology is further proposed. This methodology is developed with the aim of being implemented for the design of FD SOI circuits. It consists in using the same device dimensions and bias currents for the bulk and the corresponding FD SOI design. The analysis performed proves that such an approach permits one to obtain better circuit performances using the FD SOI technology. The EKV model is chosen for Spice simulations. For that purpose the extraction of the EKV intrinsic parameters has been performed for the experimental 0.5 μm FD SOI technology. The EKV model card obtained from transistor measurements is implemented straightforwardly for circuit simulations. The first study presented in this thesis is an FD SOI Hall sensor front-end for energy measurement. The mixed-mode microsystem design is completely based on the proposed design methodology. The system level solutions are also included, such as the spinning-current method that serves for reduction of the offset and low frequency noise of the analog front-end, and a high resolution analog-to-digital conversion technique. The integrated microsystem is entirely functional. Furthermore, according to the existing literature, this integrated circuit is the first microsystem completely realized using FD SOI technology. The overall system error that is obtained is less than 1.5 %. During the second part of this work, a novel sensing scheme that exploits an automatic reference generation based on successive approximations has been developed for the PD SOI capacitor-less 1T DRAM. The 1T DRAM reference current is generated by an adjustable current source. The electrical calibration of the reference current is performed using a digital-to-analog converter and successive approximations algorithm. The proposed scheme is evaluated in a 2 kb test chip. The circuit integrated using PD SOI technology contains a 2 kb 1T memory array, as well as automatic reference generators and peripheral circuits. The automatic reference generator comprises current mode sense amplifier, M/3M converter, and successive approximations register. All blocks implemented in the test chip are described in detail, and PD SOI design issues are discussed. A number of experimental results demonstrate the potential of the PD SOI 1T DRAM for future embedded DRAM applications. The measured retention time under holding conditions is higher than 1s. In the continuous read mode, a few hundreds of the read cycles can be performed without a refresh operation. The test chip has a measured access time of 25 ns with a read cycle time of 70 ns.

EPFL2005

Chargement

Methodology for 3-D Substrate Network Extraction for SPICE Simulation of Parasitic Currents in Smart Power ICs

Pietro Buccella, Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci

A 3-D simulation of substrate currents is crucial to analyze parasitic coupling effects due to minority carrier injection in smart power ICs. In this paper, a substrate parasitic extraction methodology is introduced by dividing the IC layout into elementary elements to solve the continuity equation for minority carriers in the volume based on the finite-difference method. A substrate parasitic network is derived from the mesh generated through the existing mixed-signal design flow. The induced substrate model is included in circuit simulators such as SPICE to predict the effects of substrate couplings during the design phase. Furthermore, this analysis enables optimization of layout with minimal parasitic effects. By linking the substrate model to the active components, the couplings between the integrated circuit with the substrate parasitic currents can be analyzed during circuit simulations. Simulations and measurements on an high voltage driver reveal consistent results and therefore confirm the validity of the method. Therefore, the approach developed herein is effective to predict parasitic couplings due the injection of minority carriers.

Ieee-Inst Electrical Electronics Engineers Inc2016

Chargement

A novel approach for SPICE modeling of light and radiation effects in ICs

Chiara Rossi

Modeling the interaction of ionizing radiation, either light or ions, in integrated circuits is essential for the development and optimization of optoelectronic devices and of radiation-tolerant circuits. Whereas for optical sensors photogenerated carriers play an essential role, high energy ionizing particles can be a severe issue for circuits, as they create high density of excess carriers in ICs substrate, causing parasitic signals. In particular, recent advances in CMOS scaling have made circuits more sensitive to errors and dysfunctions caused by radiation-induced currents, even at the ground level. TCAD simulations of excess carriers generated by light or radiation are not dedicated to large scale circuit simulations since only few devices can be simulated at a time and computation times are too long. Conversely, SPICE simulations are faster, but their accuracy is strictly dependent on the correctness of the compact models used to describe the devices, especially when dealing with photocurrents and parasitic radiation-induced currents. The objective of this thesis is to develop a novel modeling approach for SPICE-compatible simulations of electron-hole pairs generated by light and by high energy particles. The approach proposed in this work is based on the Generalized Lumped Devices, previously developed to simulate parasitic signals in High Voltage MOSFET ICs. Here, the model is extended to include excess carriers generation. The developed approach allows physics-based simulations of semiconductor structures, hit by light or radiation, that can be run in standard circuit simulators without the need for any empirical parameter, only relying on the technological and geometrical parameters of the structure, and without any predefined compact model. The model is based on a coarse mesh of the device to obtain an equivalent network of Generalized Lumped Devices. The latter predicts generation of excess carriers and their propagation, recombination and collection at circuit nodes through the definition of equivalent voltages, proportional to the excess carrier concentrations, and equivalent currents, proportional to the excess carrier gradients. The model is validated with Sentaurus TCAD numerical simulations for different scenarios. Regarding light effects, the proposed strategy is applied to simulate various optoelectronic devices. Complete DC I-V characteristics of a solar cell and transient response of a photodiode are studied. Next, phototransistors are considered. After, a full pixel of a 3T-APS CMOS image sensor is analyzed. The photosensing device, described with Generalized Devices, is co-simulated with the in-pixel circuit, described with compact models. The impact of semiconductor parameters on pixel output and on crosstalk between adjacent pixels is predicted. Finally, radiation-induced soft errors in ICs are examined. Alpha particles at different energies hitting the substrate are simulated. Parasitic currents collected at contacts are studied as a function of particles position and energy. Funneling effect, which is a phenomenon specific to high injection, is also included in the model. This work shows that the Generalized Lumped Devices approach can be successfully used for SPICE simulations of optoelectronic devices and for prediction of radiation- induced parasitic currents in ICs substrate. This thesis is a first step towards a complete and flexible tool for excess carriers modeling in standard circuit simulators.

EPFL2021

Chargement