Concept

Barrel processor

Publications associées (10)

Improving Main-memory Database System Performance through Cooperative Multitasking

Database systems access memory either sequentially or randomly. Contrary to sequential access and despite the extensive efforts of computer architects, compiler writers, and system builders, random access to data larger than the processor cache has been s ...

EPFL2019

A Real-Time Multi-Camera Depth Estimation ASIC with Custom On-Chip Embedded DRAM

Jonathan Emmanuel D Narinx

The capability to process high-resolution videos in real-time is becoming more important in a wide variety of applications such as autonomous vehicles, virtual reality or intelligent surveillance systems. The high-accuracy and complex video processing algo ...

EPFL2019

ESTIMA: Extrapolating ScalabiliTy of In-Memory Applications

Rachid Guerraoui, Aleksandar Dragojevic, Georgios Chatzopoulos

This article presents ESTIMA, an easy-to-use tool for extrapolating the scalability of in-memory applications. ESTIMA is designed to perform a simple yet important task: Given the performance of an application on a small machine with a handful of cores, ES ...

2017

ESTIMA: Extrapolating ScalabiliTy of In-Memory Applications

Rachid Guerraoui, Aleksandar Dragojevic, Georgios Chatzopoulos

This paper presents ESTIMA, an easy-to-use tool for extrapolating the scalability of in-memory applications. ESTIMA is designed to perform a simple, yet important task: given the performance of an application on a small machine with a handful of cores, EST ...

ACM Press2016

ATraPos: Adaptive Transaction Processing on Hardware Islands

Anastasia Ailamaki, Pinar Tözün, Danica Porobic, Erietta Liarou

Nowadays, high-performance transaction processing applications increasingly run on multisocket multicore servers. Such architectures exhibit non-uniform memory access latency as well as non-uniform thread communication costs. Unfortunately, traditional sha ...

2014

Eliminating unscalable communication in transaction processing

Anastasia Ailamaki, Frederick Ryan Johnson, Ippokratis Pandis

Multicore hardware demands software parallelism. Transaction processing workloads typically exhibit high concurrency, and, thus, provide ample opportunities for parallel execution. Unfortunately, because of the characteristics of the application, transacti ...

Springer Verlag2014

SLICC: Self-Assembly of Instruction Cache Collectives for OLTP Workloads

Anastasia Ailamaki, Pinar Tözün

Online transaction processing (OLTP) is at the core of many data center applications. OLTP workloads are known to have large instruction footprints that foil existing L1 instruction caches resulting in poor overall performance. Prefetching can reduce the i ...

2012

NOC-Out: Microarchitecting a Scale-Out Processor

Babak Falsafi, Boris Robert Grot, Pejman Lotfi Kamran

Scale-out server workloads benefit from many-core processor organizations that enable high throughput thanks to abundant request-level parallelism. A key characteristic of these workloads is the large instruction footprint that exceeds the capacity of priv ...

2012

STMBench7: A Benchmark for Software Transactional Memory

Rachid Guerraoui, Michal Kapalka

Software transactional memory (STM) is a promising technique for controlling concurrency in modern multi-processor architectures. STM aims to be more scalable than coarse-grained locking and easier to use than fine-grained locks. However, STM implementatio ...

2006

FRODO: A FRamework for Open/Distributed constraint Optimization

Adrian Petcu

We present a framework for distributed combinatorial optimization. The framework is implemented in Java, and simulates a multiagent environment in a single Java virtual machine. Each agent in the environment is executed asynchronously in a separate executi ...

2006

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