Concept

Semiconductor memory

Publications associées (414)

Low-Noise Amplifier with Sample & Hold for High-Density Stimulation and Recording of Neural Signals

Pierre-André Farine, Steve Tanner, Urs Alexander Müller

In this paper, the design of a low-noise amplifier (LNA) for a 32x32 pixel microelectrode array (MEA) is presented. Its gain and noise amount to 50 dB and 10 Vrms, respectively, at a bandwidth of 66 kHz. The LNA consumes less than 85 uW. The integrated off ...

2011

Low-noise amplifier with sample & hold for high-density stimulation and recording of neural signals

Pierre-André Farine, Steve Tanner, Urs Alexander Müller

In this paper, the design of a low-noise amplifier (LNA) for a 32x32 pixel microelectrode array (MEA) is presented. Its gain and noise amount to 50 dB and 10 μVrms, respectively, at a bandwidth of 66 kHz. The LNA consumes less than 85 μW. The integrated of ...

2011

Reliability in the Dark Silicon Era

Babak Falsafi

Information technology is now an indispensable pillar of a modern-day society, thanks to the proliferation of digital platforms in the past several decades. The demand on robust and economical data processing and storage, however, is growing faster than te ...

IEEE Computer Soc Press, Customer Service Center, Po Box 3014, 10662 Los Vaqueros Circle, Los Alamitos, CA 907202011

Simulation of High-Performance Memory Allocators

David Atienza Alonso, José Luis Risco Martin

This study presents a single-core and a multi-core processor architecture for health monitoring systems where slow biosignal events and highly parallel computations exist. The single-core architecture is composed of a processing core (PC), an instruction m ...

Elsevier2011

Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing

David Atienza Alonso, Andreas Peter Burg, Luca Benini, Ahmed Yasir Dogan

Springer-Verlag Heidelberg2011

Top-down fabrication of very-high density vertically stacked silicon nanowire arrays with low temperature budget

Giovanni De Micheli, Davide Sacchetto, Michail Zervas, Yusuf Leblebici

We report on a top-down complementary metal oxide semiconductor (CMOS) compatible fabrication method of ultra-high density Si nanowire (SiNW) arrays using a time multiplexed alternating process (TMAP) with low temperature budget. The flexibility of the fab ...

Elsevier2011

Laboratory Scale Prototype of a Power Electronic Transformer for Traction Applications

Drazen Dujic, Akos Mester, Toufann Chaudhuri

Combining modern high-power semiconductor devices with constantly improving magnetic materials opens up the possibility to replace bulky low-frequency transformers with a new medium voltage medium frequency conversion structure. While there are still chall ...

2011

Cuckoo Directory: A Scalable Directory for Many-Core Systems

Babak Falsafi, Michael Ferdman, Pejman Lotfi Kamran, Ken Balet

Growing core counts have highlighted the need for scalable on-chip coherence mechanisms. The increase in the number of on-chip cores exposes the energy and area costs of scaling the directories. Duplicate-tag based directories require highly associative st ...

IEEE Press2011

Resist-assisted assembly of single-walled carbon nanotube devices with nanoscale precision

Mihai Adrian Ionescu, Ji Cao, Clemens Benedict Nyffeler

We report a novel resist-assisted dielectrophoresis method for single-walled carbon nanotube (SWCNT) assembly. It provides nanoscale control of the location, density, orientation and shape of individual SWCNTs. Sub-50 nm accuracy and a yield higher than 85 ...

Elsevier2011

A Switched Capacitor Fully Differential Correlated Double Sampling Circuit for CMOS Image Sensors

Sandro Carrara, Yusuf Leblebici, Gözen Köklü

Complementary metal oxide semiconductor (CMOS) image sensors are more compatible than charge coupled devices (CCDs) for lab-on-a-chip platforms due to their inherited advantages. However, without the noise reduction circuits, CMOS technology wouldn’t be ab ...

2011

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