Publications associées à Architecture Dataflow

Composite Data Types in Dynamic Dataflow Languages as Copyless Memory Sharing Mechanism

Marco Mattavelli, Endri Bezati, Aurélien François Gilbert Bloch

This paper presents new optimization approaches aiming at reducing the impact of memory accesses on the performance of dataflow programs. The approach is based on introducing a high level management of composite data types in dynamic dataflow programming l ...

2019

Hardware-conscious Hash-Joins on GPUs

Anastasia Ailamaki, Periklis Chrysogelos, Panagiotis Sioulas, Manolis Karpathiotakis, Raja Appuswamy

Traditionally, analytical database engines have used task parallelism provided by modern multisocket multicore CPUs for scaling query execution. Over the past few years, GPUs have started gaining traction as accelerators for processing analytical queries d ...

IEEE2019

Speculative Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic

With FPGAs facing broader application domains, the conversion of imperative languages into dataflow circuits has been recently revamped as a way to overcome the conservatism of statically scheduled high-level synthesis. Apart from the ability to extract pa ...

ASSOC COMPUTING MACHINERY2019

Execution Trace Graph of Dataflow Process Networks

Marco Mattavelli, Simone Casale Brunet

The paper introduces and specifies a formalism that provides complete representations of dataflow process network (DPN) program executions, by means of directed acyclic graphs. Such graphs, also known as execution trace graphs (ETG), are composed of nodes ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2018

High-Precision Performance Estimation for the Design Space Exploration of Dynamic Dataflow Programs

Marco Mattavelli, Simone Casale Brunet, Endri Bezati, Malgorzata Maria Michalska

The implementation and optimization of dynamic dataflow programs on multi/many-core platforms require solving a very difficult problem: how to partition and schedule the processing elements and dimension their interconnecting buffers according to given opt ...

2018

Deterministic Parallel Routing for FPGAs based on Galois Parallel Execution Model

Mirjana Stojilovic, Philip Brisk

This paper describes a deterministic and parallel implementation of the VPR routability-driven router for FPGAs. We considered two parallefization strategies: (1) routing multiple nets in parallel; and (2) routing one net at a time, while parallelizing the ...

IEEE2018

Buffer dimensioning for throughput improvement of dynamic dataflow signal processing applications on multi-core platforms

Marco Mattavelli, Simone Casale Brunet, Endri Bezati, Malgorzata Maria Michalska

Executing a dataflow program on a parallel platform requires assigning to each buffer a given size so that correct program executions take place without introducing any deadlock. Furthermore, in the case of dynamic dataflow programs, specific buffer size a ...

2017

Nonvolatile Memory Crossbar Arrays for Non-von Neumann Computing

Irem Boybat Kara, Severin Sidler, Carmelo Di Nolfo

In the conventional von Neumann (VN) architecture, data—both operands and operations to be performed on those operands—makes its way from memory to a dedicated central processor. With the end of Dennard scaling and the resulting slowdown in Moore’s law, th ...

Springer India2017

Performance Estimation Based Multicriteria Partitioning Approach for Dynamic Dataflow Programs

Marco Mattavelli, Nicolas Zufferey, Malgorzata Maria Michalska

The problem of partitioning a dataflow program onto a target architecture is a difficult challenge for any application design. In general, since the problem is NP-complete, it consists of looking for high quality solutions in terms of maximizing the achiev ...

Hindawi Limited2016

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Architecture Dataflow

Composite Data Types in Dynamic Dataflow Languages as Copyless Memory Sharing Mechanism

Hardware-conscious Hash-Joins on GPUs

Speculative Dataflow Circuits

Execution Trace Graph of Dataflow Process Networks

High-Precision Performance Estimation for the Design Space Exploration of Dynamic Dataflow Programs

Deterministic Parallel Routing for FPGAs based on Galois Parallel Execution Model

Buffer dimensioning for throughput improvement of dynamic dataflow signal processing applications on multi-core platforms

Systematic Design Space Exploration of Dynamic Dataflow Programs for Multi-core Platforms

Nonvolatile Memory Crossbar Arrays for Non-von Neumann Computing

Performance Estimation Based Multicriteria Partitioning Approach for Dynamic Dataflow Programs

Graph Chatbot

Chattez avec Graph Search

Nonvolatile Memory Crossbar Arrays for Non-von Neumann Computing

Composite Data Types in Dynamic Dataflow Languages as Copyless Memory Sharing Mechanism

Systematic Design Space Exploration of Dynamic Dataflow Programs for Multi-core Platforms

Performance Estimation Based Multicriteria Partitioning Approach for Dynamic Dataflow Programs

Hardware-conscious Hash-Joins on GPUs

Speculative Dataflow Circuits

Execution Trace Graph of Dataflow Process Networks

Buffer dimensioning for throughput improvement of dynamic dataflow signal processing applications on multi-core platforms

High-Precision Performance Estimation for the Design Space Exploration of Dynamic Dataflow Programs

Deterministic Parallel Routing for FPGAs based on Galois Parallel Execution Model