Concept

PCI Express

Publications associées (63)

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

Giovanni De Micheli, Yusuf Leblebici, Alessandro Cevrero, Giulia Beanato

3D-ICs based on TSV technology provide high bandwidth inter-chip connections. The drawback is that most of the existing TSVs consume a large amount of silicon real estate. We present circuit-level design and analysis of area efficient, low power, high-data ...

2014

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

Giovanni De Micheli, Yusuf Leblebici, Alessandro Cevrero, Giulia Beanato

2014

26.3 A pin- and power-efficient low-latency 8-to-12Gb/s/wire 8b8w-coded SerDes link for high-loss channels in 40nm technology

Mohammad Amin Shokrollahi, Christoph Walter, Harm Cronie, Anant Pratap Singh, Klaas Lammert Hofstra, Kia Salimi

The continuing demand for higher bandwidth in serial interconnects has pushed the symbol rate of differential lanes into the high-insertion-loss region of channels. Multi-level signaling such as differential PAM-4 [1] has been used to mitigate the loss of ...

2014

Die-Stacked DRAM Caches for Servers: Hit Ratio, Latency, or Bandwidth? Have It All with Footprint Cache

Babak Falsafi, Stavros Volos

Recent research advocates using large die-stacked DRAM caches to break the memory bandwidth wall. Existing DRAM cache designs fall into one of two categories — block-based and page-based. The former organize data in conventional blocks (e.g., 64B), ensurin ...

ACM2013

PHD2 regulates arteriogenic macrophages through TIE2 signalling

Michele De Palma, Mario Leonardo Squadrito, Ferdinando Pucci

Occlusion of the main arterial route redirects blood flow to the collateral circulation. We previously reported that macrophages genetically modified to express low levels of prolyl hydroxylase domain protein 2 (PHD2) display an arteriogenic phenotype, whi ...

Wiley-Blackwell2013

A 2.78 mm2 65 nm CMOS Gigabit MIMO Iterative Detection and Decoding Receiver

Andreas Peter Burg

Iterative detection and decoding (IDD), combined with spatial-multiplexing multiple-input multiple-output (MIMO) transmission, is a key technique to improve spectral efﬁciency in wireless communications. In this paper we present the—to the best of our know ...

2012

A Pragmatic Approach for Predicting the Scalability of Parallel Applications

Rachid Guerraoui, Aleksandar Dragojevic

Predicting the scalability of parallel applications is becoming crucial now that the number of cores in modern CPUs doubles roughly every two years. Traditional ways to get some understanding of the scalability of a parallel application rely on extensive e ...

EPFL2012

A High-throughput and Low-Latency Interconnection Network for Multi-Core Clusters with 3-D Stacked L2 Tightly-Coupled Data Memory

Giovanni De Micheli, Luca Benini

The performance of most digital systems today is limited by the interconnect latency between logic and memory, rather than by the performance of logic or memory itself. Three- dimensional (3-D) integration using through-silicon-vias (TSVs) may provide a so ...

2012

Integration of Engineered Source and Drain Extensions in Double Gate Mosfet with Sub-32nm Channel Length

Jyotshna Bhandari

Since the advent of CMOS technology, the semiconductor industry has been successful in achieving continuously improved performance. The feature size of the most important electronic device, the Metal Oxide Semiconductor Field Effect Transistor (MOSFET), ha ...

EPFL2011

Realization and Characterization of MEMS-Based Programmable Slit Mask for Multi-Object Spectroscopy

Nico de Rooij, Michael David Canonica, Wilfried Noell

Multi-object spectroscopy (MOS) is a powerful tool for space and ground-based telescopes for studying the formation of galaxies. This technique requires a programmable slit mask for astronomical object selection. A first sample of MEMS-based programmable r ...

Spie-Int Soc Optical Engineering, Po Box 10, Bellingham, Wa 98227-0010 Usa2010

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