Publications associées à Via traversant

Design and Analysis of NoCs for Low-Power 2D and 3D SoCs

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu

Networks-on-Chip (NoC), being a system-level interconnect, can play a major role in achieving low-power SoC designs. In many designs, the cores are grouped in to Voltage Islands (VIs). To reduce the leakage power consumption, an island containing cores tha ...

Springer New York2011

CELONCEL: Effective Design Technique for 3-D Monolithic Integration targeting High Performance Integrated Circuits

Giovanni De Micheli, Shashi Kanth Bobba, Thomas Ernst

3-D monolithic integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. Since the device layers are processed in sequential order, the size of the vertical contacts is similar to traditional contac ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2011

Design Methods and Tools for 3D Integration

Giovanni De Micheli, David Atienza Alonso, Yusuf Leblebici, Vasileios Pavlidis

The design of 3-dimensional integrated circuits requires new specialized tools, methods and flows. Whereas some tools are on the market and some design flows for standard ICs are extended to handle die stacking and through-silicon vias, much R&D has still ...

2011

Addressable MEMS slit mask for multi-object spectroscopy based on multi-wafer stacking

Nico de Rooij, Michael David Canonica, Wilfried Noell

MEMS-based programmable slit masks are developed for multi-object spectroscopy in astronomy. Devices with 2048 tiltable micromirrors were fabricated using multiple wafer-level bonding and implemented with individual addressing of each element. ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2011

Thermal Modeling and Management of Liquid-Cooled 3D Stacked Architectures

David Atienza Alonso, Ayse Kivilcim Coskun

3D stacked architectures are getting increasingly attractive as they improve yield, reduce interconnect power and latency, and enable integrating layers manufactured with different technologies on the same chip. However, 3D integration results in higher te ...

Jürgen Becker, Marcelo Johann, Ricardo Reis2011

3D Integration Technology for Lab-on-a-Chip Applications

Carlotta Guiducci, Yusuf Leblebici, Yüksel Temiz, Samuel Kilchenmann

A review is presented of advances and challenges in fully integrated systems for personalised medicine applications. One key issue for the commercialisation of such systems is the disposability of the assay-substrate at a low cost. This work adds a new dim ...

Institution of Engineering and Technology2011

CCNoC: On-Chip Interconnects for Cache-Coherent Manycore Server Chips

Giovanni De Micheli, Babak Falsafi, Ciprian Seiculescu, Stavros Volos, Naser Khosro Pour

Manycore chips are emerging as the architecture of choice to provide power-scalability and improve performance while riding the Moore’s law. On-chip interconnects are increasingly playing a pivotal role in power- and performance- scalability of such microa ...

2011

Low material budget microfabricated cooling devices for particle detectors and front-end electronics

Philippe Renaud, Alessandro Mapelli, Harald Van Lintel

Novel cooling systems with very low material budget are being fabricated and studied. They consist of silicon wafers in which microchannels are etched and closed by bonding another wafer. This cooling option is being considered for future HEP detectors of ...

2011

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Via traversant

Design and Analysis of NoCs for Low-Power 2D and 3D SoCs

CELONCEL: Effective Design Technique for 3-D Monolithic Integration targeting High Performance Integrated Circuits

Design Methods and Tools for 3D Integration

Addressable MEMS slit mask for multi-object spectroscopy based on multi-wafer stacking

Thermal Modeling and Management of Liquid-Cooled 3D Stacked Architectures

3D Integration Technology for Lab-on-a-Chip Applications

In-IC Strategies for 3D Devices in Bulk Silicon

CCNoC: On-Chip Interconnects for Cache-Coherent Manycore Server Chips

Clock Distribution Networks in 3-D Integrated Systems

Low material budget microfabricated cooling devices for particle detectors and front-end electronics

Graph Chatbot

Chattez avec Graph Search

Design and Analysis of NoCs for Low-Power 2D and 3D SoCs

CELONCEL: Effective Design Technique for 3-D Monolithic Integration targeting High Performance Integrated Circuits

Design Methods and Tools for 3D Integration

Addressable MEMS slit mask for multi-object spectroscopy based on multi-wafer stacking

Thermal Modeling and Management of Liquid-Cooled 3D Stacked Architectures

3D Integration Technology for Lab-on-a-Chip Applications

In-IC Strategies for 3D Devices in Bulk Silicon

CCNoC: On-Chip Interconnects for Cache-Coherent Manycore Server Chips

Clock Distribution Networks in 3-D Integrated Systems

Low material budget microfabricated cooling devices for particle detectors and front-end electronics