Algorithme de TomasuloL’algorithme de Tomasulo est un algorithme facilitant le parallélisme au sein des processeurs mis au point en 1967 par Robert Tomasulo. Cet algorithme, est l'une des implémentations possibles pour l'exécution dans le désordre : il trie les instructions de manière à traiter plus tard les instructions qui seraient normalement bloquées en raison de dépendances de données. Mise en place pour la première fois pour l'unité de calcul en virgule flottante de l'IBM 360 modèle 90. Robert Tomasulo a reçu le Prix Eckert-Mauchly en 1997 pour cet algorithme.
Loi de GustafsonEn architecture informatique, la loi de Gustafson donne l'accélération théorique en latence de l'exécution d'une tâche à temps d'exécution constant que l'on peut attendre d'un système dont on améliore les ressources. Elle est énoncée par l'informaticien John L. Gustafson et son collègue Edwin H. Barsis dans l'article Reevaluating Amdahl's Law en 1988.
Uniform memory accessUniform memory access (UMA) is a shared memory architecture used in parallel computers. All the processors in the UMA model share the physical memory uniformly. In an UMA architecture, access time to a memory location is independent of which processor makes the request or which memory chip contains the transferred data. Uniform memory access computer architectures are often contrasted with non-uniform memory access (NUMA) architectures. In the NUMA architecture, each processor may use a private cache.
Barrière de synchronisationEn programmation concurrente, une barrière de synchronisation permet de garantir qu'un certain nombre de tâches aient passé un point spécifique. Ainsi, chaque tâche qui arrivera sur cette barrière devra attendre jusqu'à ce que le nombre spécifié de tâches soient arrivées à cette barrière. Pour réaliser ce premier algorithme de barrière de synchronisation, il faut disposer de deux sémaphores et d'une variable : Un sémaphore MUTEX (initialisé à 1) protégeant la variable.
4-bit computing4-bit computing is the use of computer architectures in which integers and other data units are 4 bits wide. 4-bit central processing unit (CPU) and arithmetic logic unit (ALU) architectures are those that are based on registers or data buses of that size. Memory addresses (and thus address buses) for 4-bit CPUs are generally much larger than 4-bit (since only 16 memory locations would be very restrictive), such as 12-bit or more, while they could in theory be 8-bit. A group of four bits is also called a nibble and has 24 = 16 possible values.
Instruction cycleThe instruction cycle (also known as the fetch–decode–execute cycle, or simply the fetch-execute cycle) is the cycle that the central processing unit (CPU) follows from boot-up until the computer has shut down in order to process instructions. It is composed of three main stages: the fetch stage, the decode stage, and the execute stage. In simpler CPUs, the instruction cycle is executed sequentially, each instruction being processed before the next one is started.
Temporal multithreadingTemporal multithreading is one of the two main forms of multithreading that can be implemented on computer processor hardware, the other being simultaneous multithreading. The distinguishing difference between the two forms is the maximum number of concurrent threads that can execute in any given pipeline stage in a given cycle. In temporal multithreading the number is one, while in simultaneous multithreading the number is greater than one. Some authors use the term super-threading synonymously.
Directive (programming)In computer programming, a directive or pragma (from "pragmatic") is a language construct that specifies how a compiler (or other translator) should process its input. Directives are not part of the grammar of a programming language, and may vary from compiler to compiler. They can be processed by a preprocessor to specify compiler behavior, or function as a form of in-band parameterization. In some cases directives specify global behavior, while in other cases they only affect a local section, such as a block of programming code.
