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Concept

Banc de registres

Dans un processeur, un banc de registres est une mémoire interne au processeur, dans laquelle sont rassemblés certains (voire la totalité) des registres du processeur. En anglais, on parle de register file. Dans les microprocesseurs, les bancs de registres sont généralement réalisés à l'aide de RAM statique (bascules). Banc de registre simple port thumb|Banc de registre Un bancs de registre contient une entrée d'adresse sur laquelle on place une suite de bits qui permet d'identifier le registre à sélectionner. Cette suite de bits n'est autre que le nom du registre en question. Sur les processeurs avec un banc de registres, on peut voir le nom d'un registre comme une sorte d'adresse permettant d'identifier un registre dans le banc de registres. Il ne faut pas oublier que certains registres n'ont pas de noms : le Program Counter, le registre d'état, etc. Ceux-ci ne sont pas forcément rassemblés avec les autres registres et sont souvent intégrés dans des circuits spécial

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Central processing unit

A central processing unit (CPU)—also called a central processor or main processor—is the most important processor in a given computer. Its electronic circuitry executes instructions of a computer pr

Registre de processeur

Un registre est un emplacement de mémoire interne à un processeur. Les registres se situent au sommet de la hiérarchie mémoire : il s'agit de la mémoire la plus rapide d'un ordinateur, mais dont le c

Microarchitecture

Wearout-Aware Compiler-Directed Register Assignment for Embedded Systems

David Atienza Alonso

Although constant technology scaling has resulted in considerable benefits, smaller device dimensions, higher operating temperatures and electric fields have also contributed to faster device aging due to wearout. Not only does this result in the shortening of processor lifetimes, it leads to faster wearout resultant performance degradation with operating time. Instead of taking a reactive approach towards reliability awareness, we propose a pre-emptive route toward wearout mitigation. Given the significant thermal and stress variation across the components of microprocessors, in this work we focus on one of the most likely candidates for overheating and hence reliability failures, the register file. We propose different wearout-aware compiler-directed register assignment techniques that distribute the stress induced wearout throughout the register file, with the aim of improving the lifetime of the register file, with negligible performance overhead. We compare our results with a state-of-the-art thermal-aware compilation scheme to show the clear advantage our proposed wearout-aware scheme has over thermal-aware schemes in terms of lifetime improvement that can reach up to 20% for Bias Temperature Instability.

IEEE Press2012

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Energy-Aware Compilation and Hardware Design for VLIW Embedded Systems

David Atienza Alonso, José Luis Ayala Rodrigo

Tomorrow's embedded devices need to run multimedia applications demanding high computational power with low energy consumption constraints. In this context, the register file is a key source of power consumption and its inappropriate design and management severely affects system power. In this paper, we present a new approach to reduce the energy of shared register files in forthcoming embedded VLIW processors running real-life applications up to 60% without performance penalty. This approach relies on limited hardware extensions and a compiler-based energy-aware register assignment algorithm to deactivate at run-time parts of the register file (i.e., sub-banks) in an independent way.

2007

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Compilation for Delay Impact Minimization in VLIW Embedded Systems

David Atienza Alonso, José Luis Ayala Rodrigo

Tomorrow’s embedded devices need to run high resolution multimedia as well as need to support multistandard wireless systems which require an enormous computational complexity with a very low energy consumption and very high performance constraints. In this context, the register file is one of the key sources of power consumption and performance bottleneck, and its inappropriate design and management can severely affect the performance of the system. In this paper, we present a new compilation approach to mitigate the performance implications of technology variation in the shared register file in upcoming embedded VLIW architectures with several processing units. The compilation approach is based on a redefined register assignment policy and a set of architectural modifications to this device. Experimental results show up to a 67% performance improvement with our technique.

IEEE Press2006

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EE-390(a): Lab on hardware-software digital systems codesign

During the course, we cover the design of multi-core embedded systems running Linux on an FPGA. Students learn how to develop hardware-software co-design solutions for complex tasks using high-level synthesis languages. We cover debugging co-designed embedded systems with integrated logic analyzers.

CS-307: Introduction to multiprocessor architecture

Multiprocessors are a core component in all types of computing infrastructure, from phones to datacenters. This course will build on the prerequisites of processor design and concurrency to introduce the essential technologies required to combine multiple processing elements into a single computer.

CS-420: Advanced compiler construction

Students learn several implementation techniques for modern functional and object-oriented programming languages. They put some of them into practice by developing key parts of a compiler and run time system for a simple functional programming language.