Publications associées à Embarrassingly parallel

Spatio-Temporal Regularization Of Flow-Fields

Michaël Unser, Nikolaos Stergiopoulos, Emrah Bostan, Pouya Dehghani Tafti, Orestis Vardoulis, Davide Piccini

We introduce a novel variational framework for the regularized reconstruction of time-resolved volumetric flow fields. Our objective functional takes the physical characteristics of the underlying flow into account in both the spatial and the temporal doma ...

IEEE2013

Design Methods for Parallel Hardware Implementation of Multimedia Iterative Algorithms

David Atienza Alonso, Ivan Beretta, Alessandro Antonio Nacci

Traditionally, parallel implementations of multimedia algorithms are carried out manually, since the automation of this task is very difficult due to the complex dependencies that generally exist between different elements of the data set. Moreover, there ...

Institute of Electrical and Electronics Engineers2013

Practical parallel rendering of detailed neuron simulations

John Anthony Biddiscombe

Parallel rendering of large polygonal models with transparency is challenging due to the need for alpha-correct blending and compositing, which is costly for very large models with high depth complexity and spatial overlap. In this paper we compare the per ...

Eurographics Association2013

Synchronizing Code Execution on Ultra-Low-Power Embedded Multi-Channel Signal Analysis Platforms

David Atienza Alonso, Andreas Peter Burg, Giovanni Ansaloni, Ruben Braojos Lopez, Jeremy Hugues-Felix Constantin, Ahmed Yasir Dogan

Embedded biosignal analysis involves a considerable amount of parallel computations, which can be exploited by employing low-voltage and ultra-low-power (ULP) parallel computing architectures. By allowing data and instruction broadcasting, single instructi ...

2013

An integrated, programming model-driven framework for NoC-QoS support in cluster-based embedded many-cores

Giovanni De Micheli, Luca Benini, Federico Angiolini, Jaime Joven Murillo

Embedded SoC designs are embracing the many-core paradigm to deliver the required performance to run an ever-increasing number of applications in parallel. Networks-on-Chip (NoC) are considered as a convenient technology to implement many-core embedded pla ...

Elsevier2013

Design Space Exploration of High Level Stream Programs on Parallel Architectures: A focus on the Buffer Size Minimization and Optimization Problem

Marco Mattavelli, Simone Casale Brunet, Claudio Paolo Alberti

This paper presents a dataflow design methodology and an associated co-exploration environment, focusing on the optimization of buffer sizes. The approach is applicable to dynamic dataflow designs and its performance is presented and validated by experimen ...

2013

A 3D architecture platform dedicated to high-speed computation for power system

Maher Kayal, Laurent Fabre, Ira Nagel, Theodoros Kyriakidis, Guillaume Olivier Lanz, Denis Sallin

This paper presents an innovative 3D hardware architecture for power system dynamic and transient stability. Based on an intrinsic parallel architecture by means of mixedsignal circuits (analog and digital) it overcomes the speed of numerical simulators fo ...

2013

A Pragmatic Approach for Predicting the Scalability of Parallel Applications

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Predicting the scalability of parallel applications is becoming crucial now that the number of cores in modern CPUs doubles roughly every two years. Traditional ways to get some understanding of the scalability of a parallel application rely on extensive e ...

EPFL2012

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Embarrassingly parallel

Spatio-Temporal Regularization Of Flow-Fields

Design Methods for Parallel Hardware Implementation of Multimedia Iterative Algorithms

Practical parallel rendering of detailed neuron simulations

Synchronizing Code Execution on Ultra-Low-Power Embedded Multi-Channel Signal Analysis Platforms

Parallel algorithms and efficient implementation techniques for finite element approximations

Parallel Preconditioners for Navier-Stokes Equations and Fluid-Structure Interaction Problems

An integrated, programming model-driven framework for NoC-QoS support in cluster-based embedded many-cores

Design Space Exploration of High Level Stream Programs on Parallel Architectures: A focus on the Buffer Size Minimization and Optimization Problem

A 3D architecture platform dedicated to high-speed computation for power system

A Pragmatic Approach for Predicting the Scalability of Parallel Applications

Graph Chatbot

Chattez avec Graph Search

Spatio-Temporal Regularization Of Flow-Fields

Design Methods for Parallel Hardware Implementation of Multimedia Iterative Algorithms

Practical parallel rendering of detailed neuron simulations

Synchronizing Code Execution on Ultra-Low-Power Embedded Multi-Channel Signal Analysis Platforms

Parallel algorithms and efficient implementation techniques for finite element approximations

Design Space Exploration of High Level Stream Programs on Parallel Architectures: A focus on the Buffer Size Minimization and Optimization Problem

Parallel Preconditioners for Navier-Stokes Equations and Fluid-Structure Interaction Problems

An integrated, programming model-driven framework for NoC-QoS support in cluster-based embedded many-cores

A Pragmatic Approach for Predicting the Scalability of Parallel Applications

A 3D architecture platform dedicated to high-speed computation for power system